<< ":\n");
std::map<unsigned, BitVector> RenameRegisterMap;
unsigned SuperReg = 0;
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- unsigned Reg = Regs[i];
+ for (unsigned Reg : Regs) {
if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
SuperReg = Reg;
}
// All group registers should be a subreg of SuperReg.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- unsigned Reg = Regs[i];
+ for (unsigned Reg : Regs) {
if (Reg == SuperReg) continue;
bool IsSub = TRI->isSubRegister(SuperReg, Reg);
// FIXME: remove this once PR18663 has been properly fixed. For now,
// For each referenced group register (which must be a SuperReg or
// a subregister of SuperReg), find the corresponding subregister
// of NewSuperReg and make sure it is free to be renamed.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- unsigned Reg = Regs[i];
+ for (unsigned Reg : Regs) {
unsigned NewReg = 0;
if (Reg == SuperReg) {
NewReg = NewSuperReg;
// If this is a large problem, avoid visiting the same basic blocks multiple
// times.
if (MergePotentials.size() == TailMergeThreshold)
- for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i)
- TriedMerging.insert(MergePotentials[i].getBlock());
+ for (MergePotentialsElt &Elt : MergePotentials)
+ TriedMerging.insert(Elt.getBlock());
if (MergePotentials.size() >= 2)
MadeChange |= TryTailMergeBlocks(IBB, PredBB, MinCommonTailLength);
TargetLowering::AsmOperandInfoVector TargetConstraints =
TLI.ParseConstraints(F->getParent()->getDataLayout(), &TRI, *CI);
- for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
- TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
-
+ for (TargetLowering::AsmOperandInfo &OpInfo : TargetConstraints) {
// Compute the constraint code and ConstraintType to use.
TLI.ComputeConstraintToUse(OpInfo, SDValue());
TargetLowering::AsmOperandInfoVector TargetConstraints =
TLI->ParseConstraints(*DL, TRI, *CS);
unsigned ArgNo = 0;
- for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
- TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
-
+ for (TargetLowering::AsmOperandInfo &OpInfo : TargetConstraints) {
// Compute the constraint code and ConstraintType to use.
TLI->ComputeConstraintToUse(OpInfo, SDValue());
const TargetRegisterClass *RC,
SmallVectorImpl<unsigned> &Forbid) {
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
- for (unsigned i = 0; i != Order.size(); ++i) {
- unsigned NewReg = Order[i];
+ for (unsigned NewReg : Order) {
// Don't replace a register with itself.
if (NewReg == AntiDepReg) continue;
// Don't replace a register with one that was recently used to repair
bool Changed = false;
// Walk through the block bottom-up, looking for merging candidates.
StoreMergeCandidate Candidate;
- for (auto II = MBB.rbegin(), IE = MBB.rend(); II != IE; ++II) {
- MachineInstr &MI = *II;
+ for (MachineInstr &MI : llvm::reverse(MBB)) {
if (InstsToErase.contains(&MI))
continue;
- if (auto StoreMI = dyn_cast<GStore>(&*II)) {
+ if (auto *StoreMI = dyn_cast<GStore>(&MI)) {
// We have a G_STORE. Add it to the candidate if it writes to an adjacent
// address.
if (!addStoreToCandidate(*StoreMI, Candidate)) {
LIUArray = liuarray;
TRI = tri;
reinitPhysRegEntries();
- for (unsigned i = 0; i != CacheEntries; ++i)
- Entries[i].clear(mf, indexes, lis);
+ for (Entry &E : Entries)
+ E.clear(mf, indexes, lis);
}
InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) {
std::array<unsigned, 4> CandidateSizes = {64, 32, 16, 8};
Optional<ValueIDNum> Result = None;
Optional<LocIdx> SpillLoc = None;
- for (unsigned int I = 0; I < CandidateSizes.size(); ++I) {
- unsigned SpillID = MTracker->getLocID(SpillNo, {CandidateSizes[I], 0});
+ for (unsigned CS : CandidateSizes) {
+ unsigned SpillID = MTracker->getLocID(SpillNo, {CS, 0});
SpillLoc = MTracker->getSpillMLoc(SpillID);
ValueIDNum Val = MTracker->readMLoc(*SpillLoc);
// If this value was defined in it's own position, then it was probably
static VarLoc CreateCopyLoc(const VarLoc &OldVL, const MachineLoc &OldML,
Register NewReg) {
VarLoc VL = OldVL;
- for (size_t I = 0, E = VL.Locs.size(); I < E; ++I)
- if (VL.Locs[I] == OldML) {
- VL.Locs[I].Kind = MachineLocKind::RegisterKind;
- VL.Locs[I].Value.RegNo = NewReg;
+ for (MachineLoc &ML : VL.Locs)
+ if (ML == OldML) {
+ ML.Kind = MachineLocKind::RegisterKind;
+ ML.Value.RegNo = NewReg;
return VL;
}
llvm_unreachable("Should have found OldML in new VarLoc.");
static VarLoc CreateSpillLoc(const VarLoc &OldVL, const MachineLoc &OldML,
unsigned SpillBase, StackOffset SpillOffset) {
VarLoc VL = OldVL;
- for (int I = 0, E = VL.Locs.size(); I < E; ++I)
- if (VL.Locs[I] == OldML) {
- VL.Locs[I].Kind = MachineLocKind::SpillLocKind;
- VL.Locs[I].Value.SpillLocation = {SpillBase, SpillOffset};
+ for (MachineLoc &ML : VL.Locs)
+ if (ML == OldML) {
+ ML.Kind = MachineLocKind::SpillLocKind;
+ ML.Value.SpillLocation = {SpillBase, SpillOffset};
return VL;
}
llvm_unreachable("Should have found OldML in new VarLoc.");
bool DidChange = false;
LocMap::iterator LocMapI;
LocMapI.setMap(locInts);
- for (unsigned i = 0; i != NewRegs.size(); ++i) {
- LiveInterval *LI = &LIS.getInterval(NewRegs[i]);
+ for (Register NewReg : NewRegs) {
+ LiveInterval *LI = &LIS.getInterval(NewReg);
if (LI->empty())
continue;
// Map all of the new virtual registers.
UserValue *UV = lookupVirtReg(OldReg);
- for (unsigned i = 0; i != NewRegs.size(); ++i)
- mapVirtReg(NewRegs[i], UV);
+ for (Register NewReg : NewRegs)
+ mapVirtReg(NewReg, UV);
}
void LiveDebugVariables::
}
#ifndef NDEBUG
- for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
- assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
+ for (MachineInstr *Kill : VRInfo.Kills)
+ assert(Kill->getParent() != MBB && "entry should be at end!");
#endif
// This situation can occur:
MachineBasicBlock *MBB = MI.getParent();
// Process all uses.
- for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
- unsigned MOReg = UseRegs[i];
+ for (unsigned MOReg : UseRegs) {
if (Register::isVirtualRegister(MOReg))
HandleVirtRegUse(MOReg, MBB, MI);
else if (!MRI->isReserved(MOReg))
}
// Process all masked registers. (Call clobbers).
- for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
- HandleRegMask(MI.getOperand(RegMasks[i]));
+ for (unsigned Mask : RegMasks)
+ HandleRegMask(MI.getOperand(Mask));
// Process all defs.
- for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
- unsigned MOReg = DefRegs[i];
+ for (unsigned MOReg : DefRegs) {
if (Register::isVirtualRegister(MOReg))
HandleVirtRegDef(MOReg, MI);
else if (!MRI->isReserved(MOReg))
void MachineTraceMetrics::releaseMemory() {
MF = nullptr;
BlockInfo.clear();
- for (unsigned i = 0; i != TS_NumStrategies; ++i) {
- delete Ensembles[i];
- Ensembles[i] = nullptr;
+ for (Ensemble *&E : Ensembles) {
+ delete E;
+ E = nullptr;
}
}
LLVM_DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB)
<< '\n');
BlockInfo[MBB->getNumber()].invalidate();
- for (unsigned i = 0; i != TS_NumStrategies; ++i)
- if (Ensembles[i])
- Ensembles[i]->invalidate(MBB);
+ for (Ensemble *E : Ensembles)
+ if (E)
+ E->invalidate(MBB);
}
void MachineTraceMetrics::verifyAnalysis() const {
return;
#ifndef NDEBUG
assert(BlockInfo.size() == MF->getNumBlockIDs() && "Outdated BlockInfo size");
- for (unsigned i = 0; i != TS_NumStrategies; ++i)
- if (Ensembles[i])
- Ensembles[i]->verify();
+ for (Ensemble *E : Ensembles)
+ if (E)
+ E->verify();
#endif
}
for (unsigned K = 0; K != PRDepths.size(); ++K)
PRMax = std::max(PRMax, PRDepths[K] + PRCycles[K]);
} else {
- for (unsigned K = 0; K != PRDepths.size(); ++K)
- PRMax = std::max(PRMax, PRDepths[K]);
+ for (unsigned PRD : PRDepths)
+ PRMax = std::max(PRMax, PRD);
}
// Convert to cycle count.
PRMax = TE.MTM.getCycles(PRMax);