((op, 'a'), 0.0, 'info->stage == MESA_SHADER_COMPUTE && info->cs.derivative_group == DERIVATIVE_GROUP_NONE')
]
+# Some optimizations for ir3-specific instructions.
+optimizations += [
+ # 'al * bl': If either 'al' or 'bl' is zero, return zero.
+ (('umul_low', '#a(is_lower_half_zero)', 'b'), (0)),
+ # '(ah * bl) << 16 + c': If either 'ah' or 'bl' is zero, return 'c'.
+ (('imadsh_mix16', '#a@32(is_upper_half_zero)', 'b@32', 'c@32'), ('c')),
+ (('imadsh_mix16', 'a@32', '#b@32(is_lower_half_zero)', 'c@32'), ('c')),
+]
+
# This section contains "late" optimizations that should be run before
# creating ffmas and calling regular optimizations for the final time.
# Optimizations should go here if they help code generation and conflict
return false;
}
+/**
+ * Returns true if a NIR ALU src represents a constant integer
+ * of either 32 or 64 bits, and the higher word (bit-size / 2)
+ * of all its components is zero.
+ */
+static inline bool
+is_upper_half_zero(nir_alu_instr *instr, unsigned src,
+ unsigned num_components, const uint8_t *swizzle)
+{
+ if (nir_src_as_const_value(instr->src[src].src) == NULL)
+ return false;
+
+ for (unsigned i = 0; i < num_components; i++) {
+ unsigned half_bit_size = nir_src_bit_size(instr->src[src].src) / 2;
+ uint32_t high_bits = ((1 << half_bit_size) - 1) << half_bit_size;
+ if ((nir_src_comp_as_uint(instr->src[src].src,
+ swizzle[i]) & high_bits) != 0) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+/**
+ * Returns true if a NIR ALU src represents a constant integer
+ * of either 32 or 64 bits, and the lower word (bit-size / 2)
+ * of all its components is zero.
+ */
+static inline bool
+is_lower_half_zero(nir_alu_instr *instr, unsigned src,
+ unsigned num_components, const uint8_t *swizzle)
+{
+ if (nir_src_as_const_value(instr->src[src].src) == NULL)
+ return false;
+
+ for (unsigned i = 0; i < num_components; i++) {
+ uint32_t low_bits =
+ (1 << (nir_src_bit_size(instr->src[src].src) / 2)) - 1;
+ if ((nir_src_comp_as_int(instr->src[src].src, swizzle[i]) & low_bits) != 0)
+ return false;
+ }
+
+ return true;
+}
+
#endif /* _NIR_SEARCH_ */