lcd: add tablet mode lvds & vbyone support for tl1 [1/1]

PD#TV-2080

Problem:
need tablet mode support for tl1

Solution:
add tablet mode support for tl1

Verify:
x301

Change-Id: Ic7a6ae94255b6152236ab0d991bce9d748d670ac
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.h b/drivers/amlogic/media/vout/lcd/lcd_common.h
index 54441aa..5ff975d 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_common.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_common.h
@@ -35,7 +35,8 @@
 /* 20181012: tl1 support tcon */
 /* 20181212: tl1 update p2p config and pll setting */
 /* 20181225: update phy config */
-#define LCD_DRV_VERSION    "20181225"
+/* 20190108: tl1 support tablet mode */
+#define LCD_DRV_VERSION    "20190108"
 
 #define VPP_OUT_SATURATE            (1 << 0)
 

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
index e55447a..9c7b87e 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
@@ -232,7 +232,20 @@ static void lcd_ttl_control_set(struct lcd_config_s *pconf)
 
 static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
 {
+       struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
        unsigned int phy_div;
+       unsigned int reg_cntl0, reg_cntl1;
+
+       switch (lcd_drv->data->chip_type) {
+       case LCD_CHIP_TL1:
+               reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
+               reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
+               break;
+       default:
+               reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
+               reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
+               break;
+       }
 
        if (pconf->lcd_control.lvds_config->dual_port)
                phy_div = 2;
@@ -240,23 +253,32 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
                phy_div = 1;
 
        /* set fifo_clk_sel: div 7 */
-       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
+       lcd_hiu_write(reg_cntl0, (1 << 6));
        /* set cntl_ser_en:  8-channel to 1 */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+       lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
+       switch (lcd_drv->data->chip_type) { /* pn swap */
+       case LCD_CHIP_TL1:
+               lcd_hiu_setb(reg_cntl0, 1, 2, 1);
+               break;
+       default:
+               break;
+       }
 
        /* decoupling fifo enable, gated clock enable */
-       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
+       lcd_hiu_write(reg_cntl1,
                (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
        /* decoupling fifo write enable after fifo enable */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+       lcd_hiu_setb(reg_cntl1, 1, 31, 1);
 }
 
 static void lcd_lvds_control_set(struct lcd_config_s *pconf)
 {
+       struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
        unsigned int bit_num = 1;
        unsigned int pn_swap, port_swap, lane_reverse;
        unsigned int dual_port, fifo_mode;
        unsigned int lvds_repack = 1;
+       unsigned int ch_swap0, ch_swap1, ch_swap2;
 
        if (lcd_debug_print_flag)
                LCDPR("%s\n", __func__);
@@ -303,10 +325,21 @@ static void lcd_lvds_control_set(struct lcd_config_s *pconf)
                (1 << 12) |     /* g_select  //0:R, 1:G, 2:B, 3:0 */
                (2 << 14));     /* b_select  //0:R, 1:G, 2:B, 3:0 */
 
-       lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
-
-       if (lane_reverse)
-               lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
+       switch (lcd_drv->data->chip_type) {
+       case LCD_CHIP_TL1:
+               ch_swap0 = 0x3210;
+               ch_swap1 = 0x7654;
+               ch_swap2 = 0xba98;
+               lcd_vcbus_write(LVDS_CH_SWAP0, ch_swap0);
+               lcd_vcbus_write(LVDS_CH_SWAP1, ch_swap1);
+               lcd_vcbus_write(LVDS_CH_SWAP2, ch_swap2);
+               break;
+       default:
+               lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
+               if (lane_reverse)
+                       lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
+               break;
+       }
 
        lcd_vcbus_write(LVDS_GEN_CNTL,
                (lcd_vcbus_read(LVDS_GEN_CNTL) |
@@ -333,6 +366,19 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
 {
        unsigned int lcd_bits;
        unsigned int div_sel, phy_div;
+       struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+       unsigned int reg_cntl0, reg_cntl1;
+
+       switch (lcd_drv->data->chip_type) {
+       case LCD_CHIP_TL1:
+               reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
+               reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
+               break;
+       default:
+               reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
+               reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
+               break;
+       }
 
        phy_div = pconf->lcd_control.vbyone_config->phy_div;
        lcd_bits = pconf->lcd_basic.lcd_bits;
@@ -352,20 +398,28 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
                break;
        }
        /* set fifo_clk_sel */
-       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
+       lcd_hiu_write(reg_cntl0, (div_sel << 6));
        /* set cntl_ser_en:  8-channel to 1 */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+       lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
+       switch (lcd_drv->data->chip_type) { /* pn swap */
+       case LCD_CHIP_TL1:
+               lcd_hiu_setb(reg_cntl0, 1, 2, 1);
+               break;
+       default:
+               break;
+       }
 
        /* decoupling fifo enable, gated clock enable */
-       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
+       lcd_hiu_write(reg_cntl1,
                (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
        /* decoupling fifo write enable after fifo enable */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+       lcd_hiu_setb(reg_cntl1, 1, 31, 1);
 }
 
 static int lcd_vbyone_lanes_set(int lane_num, int byte_mode, int region_num,
                int hsize, int vsize)
 {
+       struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
        int sublane_num;
        int region_size[4];
        int tmp;
@@ -429,6 +483,16 @@ static int lcd_vbyone_lanes_set(int lane_num, int byte_mode, int region_num,
        lcd_vcbus_setb(VBO_CTRL_H, 0x1, 9, 1);
        /* lcd_vcbus_setb(VBO_CTRL_L,enable,0,1); */
 
+       switch (lcd_drv->data->chip_type) { /* pn swap */
+       case LCD_CHIP_TL1:
+               lcd_vcbus_write(LVDS_CH_SWAP0, 0x3210);
+               lcd_vcbus_write(LVDS_CH_SWAP1, 0x7654);
+               lcd_vcbus_write(LVDS_CH_SWAP2, 0xba98);
+               break;
+       default:
+               break;
+       }
+
        return 0;
 }
 
@@ -469,6 +533,7 @@ static void lcd_vbyone_wait_timing_stable(void)
 
 static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
 {
+       struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
        int lane_count, byte_mode, region_num, hsize, vsize, color_fmt;
        int vin_color, vin_bpp;
 
@@ -547,7 +612,21 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
        /* lcd_vcbus_setb(LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order */
 
        /* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
-       lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);
+       /*lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);*/
+
+       switch (lcd_drv->data->chip_type) {
+       case LCD_CHIP_TL1:
+               lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L, 0xff);
+               lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H, 0x0);
+               lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 8, 4);
+               lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 12, 4);
+               break;
+       default:
+               lcd_vcbus_write(VBO_INFILTER_CTRL, 0xff77);
+               break;
+       }
+       lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 2);
+
        lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);
 
        /*force vencl clk enable, otherwise, it might auto turn off by mipi DSI
@@ -560,6 +639,8 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
 static void lcd_vbyone_disable(void)
 {
        lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1);
+       lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 1);
+       lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1);
 }
 
 static void lcd_tablet_vbyone_wait_stable(void)
@@ -574,7 +655,7 @@ static void lcd_tablet_vbyone_wait_stable(void)
                __func__, lcd_vcbus_read(VBO_STATUS_L), (5000 - i));
 }
 
-static void lcd_vx1_wait_hpd(void)
+static void lcd_vbyone_wait_hpd(void)
 {
        int i = 0;
 
@@ -587,12 +668,17 @@ static void lcd_vx1_wait_hpd(void)
                udelay(50);
        }
        mdelay(10);
-       if (lcd_vcbus_read(VBO_STATUS_L) & 0x40)
+       if (lcd_vcbus_read(VBO_STATUS_L) & 0x40) {
                LCDPR("%s: hpd=%d\n", __func__,
                        ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 0x1));
-       else
+       } else {
                LCDPR("%s: hpd=%d, i=%d\n", __func__,
                        ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 0x1), i);
+               /* force low only actived for actual hpd is low */
+               lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 2, 2);
+       }
+
+       usleep_range(10000, 10500); /* add 10ms delay for compatibility */
 }
 
 static unsigned int vbyone_lane_num[] = {
@@ -803,7 +889,7 @@ int lcd_tablet_driver_init(void)
        case LCD_VBYONE:
                lcd_vbyone_pinmux_set(1);
                lcd_vbyone_control_set(pconf);
-               lcd_vx1_wait_hpd();
+               lcd_vbyone_wait_hpd();
                lcd_vbyone_phy_set(pconf, 1);
                lcd_tablet_vbyone_wait_stable();
                break;

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
index 89b6e7a..5fa5e39 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
@@ -346,16 +346,16 @@ static void lcd_mlvds_control_set(struct lcd_config_s *pconf)
        }
 
        /* fifo_clk_sel[7:6]: 0=div6, 1=div 7, 2=div8, 3=div10 */
-       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
+       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0_TL1, (div_sel << 6));
        /* serializer_en[27:16] */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0_TL1, 0xfff, 16, 12);
        /* pn swap[2] */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
+       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0_TL1, 1, 2, 1);
 
        /* fifo enable[30], phy_clock gating[24] */
-       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1, (1 << 30) | (1 << 24));
+       lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1_TL1, (1 << 30) | (1 << 24));
        /* fifo write enable[31] */
-       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+       lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1_TL1, 1, 31, 1);
 
        /* channel swap default no swap */
        channel_sel0 = pconf->lcd_control.mlvds_config->channel_sel0;