ARM: dts: imx: e60k02: add second uart

There is another uart next to the console uart used by vendor uboot and
kernel, enable it and document its location.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi
index 3af1ab4458ef5ee0d7c1ba82a727ff1fccde6122..cfb239d5186ac36dad68ede381350a35bdf78172 100644 (file)
--- a/arch/arm/boot/dts/e60k02.dtsi
+++ b/arch/arm/boot/dts/e60k02.dtsi
@@ -278,6 +278,12 @@
 };
 
 &uart1 {
+       /* J4, through-hole */
+       status = "okay";
+};
+
+&uart4 {
+       /* TP198, next to J4, SMD pads */
        status = "okay";
 };
 

diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
index 62d2ebda04ff7e1ae08f3b4a9bff675d5216d58d..e3f1e8d79528645b431be22d37f70873b28d1b22 100644 (file)
--- a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
@@ -94,7 +94,6 @@
                        MX6SL_PAD_KEY_ROW7__GPIO4_IO07          0x79
                        MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13       0x79
                        MX6SL_PAD_KEY_COL5__GPIO4_IO02          0x79
-                       MX6SL_PAD_KEY_ROW6__GPIO4_IO05          0x79
                >;
        };
 
@@ -160,6 +159,13 @@
                >;
        };
 
+       pinctrl_uart4: uart4grp {
+               fsl,pins = <
+                       MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
+                       MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
+               >;
+       };
+
        pinctrl_usbotg1: usbotg1grp {
                fsl,pins = <
                        MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
@@ -300,6 +306,11 @@
        pinctrl-0 = <&pinctrl_uart1>;
 };
 
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4>;
+};
+
 &usdhc2 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
        pinctrl-0 = <&pinctrl_usdhc2>;

diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
index 7214d1c982498f7cccfafabea1d10b04e9a030b7..90b32f5eb529455d2dd120f7c3e1053e31a3e129 100644 (file)
--- a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
+++ b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
@@ -104,7 +104,6 @@
                        MX6SLL_PAD_KEY_ROW7__GPIO4_IO07         0x79
                        MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13      0x79
                        MX6SLL_PAD_KEY_COL5__GPIO4_IO02         0x79
-                       MX6SLL_PAD_KEY_ROW6__GPIO4_IO05         0x79
                >;
        };
 
@@ -170,6 +169,13 @@
                >;
        };
 
+       pinctrl_uart4: uart4grp {
+               fsl,pins = <
+                       MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1
+                       MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1
+               >;
+       };
+
        pinctrl_usbotg1: usbotg1grp {
                fsl,pins = <
                        MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
@@ -302,6 +308,11 @@
        pinctrl-0 = <&pinctrl_uart1>;
 };
 
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4>;
+};
+
 &usdhc2 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
        pinctrl-0 = <&pinctrl_usdhc2>;