[(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuld")])
+(define_insn "*fmadddf"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
+ (match_operand:DF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ madbr\t%0,%1,%2
+ madb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
+(define_insn "*fmsubdf"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
+ (match_operand:DF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ msdbr\t%0,%1,%2
+ msdb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
;
; mulsf3 instruction pattern(s).
;
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuls")])
+(define_insn "*fmaddsf"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
+ (match_operand:SF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:SF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ maebr\t%0,%1,%2
+ maeb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuls")])
+
+(define_insn "*fmsubsf"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
+ (match_operand:SF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:SF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ msebr\t%0,%1,%2
+ mseb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuls")])
;;
;;- Divide and modulo instructions.