dt-bingings:uart:jh7110: add clks and reset signals to uarts

Uart uses the clock and reset framework API.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 8595cc3..42e5445 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -372,6 +372,7 @@
                        clocks = <&clkgen JH7110_UART0_CLK_CORE>,
                                        <&clkgen JH7110_UART0_CLK_APB>;
                        clock-names = "baudclk", "apb_pclk";
+                       resets = <&rstgen RSTN_U0_DW_UART_APB>;
                        interrupts = <32>;
                        status = "disabled";
                };
@@ -381,8 +382,10 @@
                        reg = <0x0 0x10010000 0x0 0x10000>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
-                       clocks = <&oscclk>, <&apb0clk>;
+                       clocks = <&clkgen JH7110_UART1_CLK_CORE>,
+                                       <&clkgen JH7110_UART1_CLK_APB>;
                        clock-names = "baudclk", "apb_pclk";
+                       resets = <&rstgen RSTN_U1_DW_UART_APB>;
                        interrupts = <33>;
                        status = "disabled";
                };
@@ -392,8 +395,10 @@
                        reg = <0x0 0x10020000 0x0 0x10000>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
-                       clocks = <&oscclk>, <&apb0clk>;
+                       clocks = <&clkgen JH7110_UART2_CLK_CORE>,
+                                       <&clkgen JH7110_UART2_CLK_APB>;
                        clock-names = "baudclk", "apb_pclk";
+                       resets = <&rstgen RSTN_U2_DW_UART_APB>;
                        interrupts = <34>;
                        status = "disabled";
                };
@@ -403,8 +408,10 @@
                        reg = <0x0 0x12000000 0x0 0x10000>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
-                       clocks = <&uartclk>, <&apb0clk>;
+                       clocks = <&clkgen JH7110_UART3_CLK_CORE>,
+                                       <&clkgen JH7110_UART3_CLK_APB>;
                        clock-names = "baudclk", "apb_pclk";
+                       resets = <&rstgen RSTN_U3_DW_UART_APB>;
                        interrupts = <45>;
                        status = "disabled";
                };
@@ -414,8 +421,10 @@
                        reg = <0x0 0x12010000 0x0 0x10000>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
-                       clocks = <&uartclk>, <&apb0clk>;
+                       clocks = <&clkgen JH7110_UART4_CLK_CORE>,
+                                       <&clkgen JH7110_UART4_CLK_APB>;
                        clock-names = "baudclk", "apb_pclk";
+                       resets = <&rstgen RSTN_U4_DW_UART_APB>;
                        interrupts = <46>;
                        status = "disabled";
                };
@@ -425,8 +434,10 @@
                        reg = <0x0 0x12020000 0x0 0x10000>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
-                       clocks = <&uartclk>, <&apb0clk>;
+                       cclocks = <&clkgen JH7110_UART5_CLK_CORE>,
+                                       <&clkgen JH7110_UART5_CLK_APB>;
                        clock-names = "baudclk", "apb_pclk";
+                       resets = <&rstgen RSTN_U5_DW_UART_APB>;
                        interrupts = <47>;
                        status = "disabled";
                };

diff --git a/arch/riscv/boot/dts/starfive/jh7110_clk.dtsi b/arch/riscv/boot/dts/starfive/jh7110_clk.dtsi
old mode 100755 (executable)
new mode 100644 (file)
index 98b1332..a98b4b8
--- a/arch/riscv/boot/dts/starfive/jh7110_clk.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110_clk.dtsi
@@ -105,12 +105,6 @@
                clock-frequency = <50000000>;
        };
 
-       uartclk: uartclk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <51200000>;
-       };
-
        dwmmc_biuclk: dwmmc_biuclk {
                compatible = "fixed-clock";
                #clock-cells = <0>;