arm64: dts: exynos: Add mem-2-mem Scaler devices

There are two Scaler devices in Exynos5433 SoCs. Add nodes for them and
their SYSMMU controllers.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I3fe7aa7fc8e48a7da3110962a723b2a84a2c34a7

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 4a5aec4f0f0129db40b35404d38410e6ebc515a6..6d8d13eeb0a887e8ed2321191e4302b25d8de2ec 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -2336,6 +2336,48 @@
                        };
                };
 
+               scaler_0: scaler@15000000 {
+                       compatible = "samsung,exynos5433-scaler";
+                       reg = <0x15000000 0x1294>;
+                       interrupts = <0 402 0>;
+                       clock-names = "pclk", "aclk", "aclk_xiu";
+                       clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
+                                <&cmu_mscl CLK_ACLK_M2MSCALER0>,
+                                <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
+                       iommus = <&sysmmu_scaler_0>;
+               };
+
+               scaler_1: scaler@15010000 {
+                       compatible = "samsung,exynos5433-scaler";
+                       reg = <0x15010000 0x1294>;
+                       interrupts = <0 403 0>;
+                       clock-names = "pclk", "aclk", "aclk_xiu";
+                       clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
+                                <&cmu_mscl CLK_ACLK_M2MSCALER1>,
+                                <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
+                       iommus = <&sysmmu_scaler_1>;
+               };
+
+               sysmmu_scaler_0: sysmmu@0x15040000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x15040000 0x1000>;
+                       interrupts = <0 404 0>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>,
+                                <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>;
+                       #iommu-cells = <0>;
+               };
+
+               sysmmu_scaler_1: sysmmu@0x15050000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x15050000 0x1000>;
+                       interrupts = <0 406 0>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>,
+                                <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>;
+                       #iommu-cells = <0>;
+               };
+
                jpeg: jpeg@15020000 {
                        compatible = "samsung,exynos5433-jpeg";
                        reg = <0x15020000 0x10000>;