- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash.
-- CONFIG_FLASH_SPANSION_S29WS_N
- s29ws-n MirrorBit flash has non-standard addresses for buffered
- write commands.
-
-- CONFIG_FLASH_VERIFY
- If defined, the content of the flash (destination) is compared
- against the source after the write operation. An error message
- will be printed when the contents are not identical.
- Please note that this option is useless in nearly all cases,
- since such flash programming errors usually are detected earlier
- while unprotecting/erasing/programming. Please only enable
- this option if you really know what you are doing.
-
- CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when
+config FSL_TRUST_ARCH_v1
+ bool
+
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
+ select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
+ ARCH_P5040 || ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
config CHAIN_OF_TRUST
select FSL_CAAM
select ARCH_MISC_INIT
+ select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
select FSL_SEC_MON
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
+config FSL_ISBC_KEY_EXT
+ bool
+ help
+ The key used for verification of next level images is picked up from
+ an Extension Table which has been verified by the ISBC (Internal
+ Secure boot Code) in boot ROM of the SoC. The feature is only
+ applicable in case of NOR boot and is not applicable in case of
+ RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
+ for all device if IE Table is copied to XIP memory Also, for
+ Layerscape, ISBC doesn't verify this table.
+
config SYS_FSL_SFP_BE
def_bool y
depends on PPC || FSL_LSCH2 || ARCH_LS1021A
#ifdef CONFIG_CHAIN_OF_TRUST
#ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_SYS_RAMBOOT
-/* The key used for verification of next level images
- * is picked up from an Extension Table which has
- * been verified by the ISBC (Internal Secure boot Code)
- * in boot ROM of the SoC.
- * The feature is only applicable in case of NOR boot and is
- * not applicable in case of RAMBOOT (NAND, SD, SPI).
- * For LS, this feature is available for all device if IE Table
- * is copied to XIP memory
- * Also, for LS, ISBC doesn't verify this table.
- */
-#define CONFIG_FSL_ISBC_KEY_EXT
-
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
/* Define the key hash here if SRK used for signing PPA image is
* different from SRK hash put in SFP used for U-Boot.
def_bool y
depends on !TARGET_SMDKV310 && !TARGET_ARNDALE
+config SPI_BOOTING
+ bool
+
config USB_BOOTING
bool
select BOARD_EARLY_INIT_F
select CPU_V7A
select SHA_HW_ACCEL
+ select SPI_BOOTING if EXYNOS5_DT
select USB_BOOTING
imply CMD_HASH
imply CRC32_VERIFY
config SYS_ETVPE_CLK
int
default 1
+
+config MAX_DSP_CPUS
+ int
+ default 12 if ARCH_B4860
+ default 2 if ARCH_B4420
endif
config SYS_L2_SIZE_256KB
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
-#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#elif defined(CONFIG_ARCH_P1021)
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
-#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_T4240)
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
-#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
-#define CONFIG_MAX_DSP_CPUS 2
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 0
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
#elif defined(CONFIG_ARCH_C29X)
-#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#define CFG_SYS_INIT_L3_ADDR 0xbff00000
#endif
#endif
-
-#if defined(CONFIG_ARCH_P3041) || \
- defined(CONFIG_ARCH_P4080) || \
- defined(CONFIG_ARCH_P5040) || \
- defined(CONFIG_ARCH_P2041)
- #define CONFIG_FSL_TRUST_ARCH_v1
-#endif
-
-#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
-/* The key used for verification of next level images
- * is picked up from an Extension Table which has
- * been verified by the ISBC (Internal Secure boot Code)
- * in boot ROM of the SoC.
- * The feature is only applicable in case of NOR boot and is
- * not applicable in case of RAMBOOT (NAND, SD, SPI).
- */
-#define CONFIG_FSL_ISBC_KEY_EXT
-#endif
#endif /* #ifdef CONFIG_NXP_ESBC */
#ifdef CONFIG_CHAIN_OF_TRUST
#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
((key_len) == 2 * KEY_SIZE_BYTES))
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
/* Global data structure */
static struct fsl_secboot_glb glb;
#endif
goto self;
}
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
static u32 check_ie(struct fsl_secboot_img_priv *img)
{
if (img->hdr.ie_flag & IE_FLAG_MASK)
{
#ifdef CONFIG_ESBC_HDR_LS
/* In LS, No SRK Flag as SRK is always present if IE not present*/
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
return !check_ie(img);
#endif
return 1;
}
#endif /* CONFIG_ESBC_HDR_LS */
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
static void install_ie_tbl(uintptr_t ie_tbl_addr,
struct fsl_secboot_img_priv *img)
case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
#endif
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
/*@fallthrough@*/
case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
key_hash = 1;
}
#endif
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
}
#endif
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (!key_found && check_ie(img)) {
ret = read_validate_ie_tbl(img);
if (ret != 0)
return -ENOMEM;
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (glb.ie_addr)
img->ie_addr = glb.ie_addr;
#endif
else
ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
-#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (!hash_cmd && check_ie(img))
ret = 0;
#endif
config BIOSEMU
bool
+ select X86EMU_RAW_IO
+
+config X86EMU_RAW_IO
+ bool
choice
prompt "Mainboard model"
if TARGET_SMDKV310
+config MIU_2BIT_INTERLEAVED
+ def_bool y
+
config SYS_BOARD
default "smdkv310"
config EXTRA_CLOCK
def_bool y
+config SERIAL_BOOT
+ def_bool y
+ depends on CF_SBF
+
config SYS_INPUT_CLKSRC
hex
default 30000000
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_SPANSION_S29WS_N=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_FLASH_VERIFY=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_FLASH_VERIFY=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SPANSION=y
+++ /dev/null
-This file documents Freescale DPAA-specific options.
-
-FMan (Frame Manager)
- - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
- on SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below:
- 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
- on SoCs T1024, etc, the notation between 10GEC and MAC as below:
- 10GEC1->MAC1, 10GEC2->MAC2
- so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on
- which 10GEC enumeration is consistent with MAC enumeration.
endif
+config FSL_SDHC_V2_3
+ bool
+
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
+ select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \
+ || ARCH_C29X
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
bool "Enable displaying empty sectors in flash info"
depends on FLASH_CFI_DRIVER
+config FLASH_SPANSION_S29WS_N
+ bool "Non-standard s29ws-n MirrorBit flash"
+ depends on FLASH_CFI_DRIVER
+ help
+ Enable this if the s29ws-n MirrorBit flash has non-standard addresses
+ for buffered write commands.
+
config FLASH_CFI_MTD
bool "Enable CFI MTD driver"
depends on FLASH_CFI_DRIVER
If the variable flashchecksum is set in the environment, perform a CRC
of the flash and print the value to console.
+config FLASH_VERIFY
+ bool "Compare writes to NOR flash with source location"
+ depends on MTD_NOR_FLASH
+ help
+ If enabled, the content of the flash (destination) is compared
+ against the source after the write operation. An error message will
+ be printed when the contents are not identical. Please note that
+ this option is useless in nearly all cases, since such flash
+ programming errors usually are detected earlier while
+ unprotecting/erasing/programming. Please only enable this option if
+ you really know what you are doing.
+
config ALTERA_QSPI
bool "Altera Generic Quad SPI Controller"
depends on DM_MTD
select SYS_FMAN_V3 if ARCH_B4420 || ARCH_B4860 || ARCH_LS1043A || \
ARCH_LS1046A || ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T2080 || ARCH_T4240
+ select FSL_FM_10GEC_REGULAR_NOTATION if ARCH_T1024
help
This driver support the Freescale FMan Ethernet controller
help
SoC has FMan v3 with mEMAC
+config FSL_FM_10GEC_REGULAR_NOTATION
+ bool
+ help
+ On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and
+ MAC as below:
+ 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
+ While on SoCs T1024, etc, the notation between 10GEC and MAC as below:
+ 10GEC1->MAC1, 10GEC2->MAC2
+ so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the
+ new SoCs on which 10GEC enumeration is consistent with MAC
+ enumeration.
+
config FTMAC100
bool "Ftmac100 Ethernet Support"
help
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_FLASH_SPANSION_S29WS_N 1
# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
#endif
"stderr=serial\0"
#define VIDEO_IO_OFFSET 0
-#define CONFIG_X86EMU_RAW_IO
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"stderr=serial\0"
#define VIDEO_IO_OFFSET 0
-#define CONFIG_X86EMU_RAW_IO
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_SYS_SPI_BASE 0x12D30000
#define FLASH_SIZE (4 << 20)
-#define CONFIG_SPI_BOOTING
#endif
/* NOR 16-bit mode */
#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
-#define CONFIG_FLASH_VERIFY
/* NOR Flash MTD */
#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
"usb_pgood_delay=40\0"
#define VIDEO_IO_OFFSET 0
-#define CONFIG_X86EMU_RAW_IO
#endif /* __CONFIG_H */
/* FLASH and environment organization */
-/* MIU (Memory Interleaving Unit) */
-#define CONFIG_MIU_2BIT_INTERLEAVED
-
#define RESERVE_BLOCK_SIZE (512)
#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
"stderr=serial,vidconsole\0"
#define VIDEO_IO_OFFSET 0
-#define CONFIG_X86EMU_RAW_IO
#endif /* __CONFIG_H */
#define CFG_SYS_DRAM_TEST
-#if defined(CONFIG_CF_SBF)
-#define CONFIG_SERIAL_BOOT
-#endif
-
/* Reserve 256 kB for Monitor */
/*
"stderr=serial\0"
#define VIDEO_IO_OFFSET 0
-#define CONFIG_X86EMU_RAW_IO
/* Environment settings */
#define CONFIG_X86_REFCODE_RUN_ADDR 0
#define VIDEO_IO_OFFSET 0
-#define CONFIG_X86EMU_RAW_IO
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vidconsole,serial\0" \
projects / platform / kernel / u-boot.git / commitdiff