int radeon_ms_agp_finish(struct drm_device *dev)
{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+
+ if (!dev_priv->bus_ready) {
+ return 0;
+ }
+ dev_priv->bus_ready = 0;
drm_agp_release(dev);
return 0;
}
uint32_t agp_status;
int ret;
+ dev_priv->bus_ready = -1;
if (dev->agp == NULL) {
DRM_ERROR("[radeon_ms] can't initialize AGP\n");
return -EINVAL;
DRM_INFO("[radeon_ms] gpu agp location 0x%08X\n",
state->mc_agp_location);
DRM_INFO("[radeon_ms] bus ready\n");
+ dev_priv->bus_ready = 1;
return 0;
}
struct radeon_pcie *pcie;
int ret = 0;
+ dev_priv->bus_ready = -1;
/* allocate and clear device private structure */
pcie = drm_alloc(sizeof(struct radeon_pcie), DRM_MEM_DRIVER);
if (pcie == NULL) {
DRM_INFO("[radeon_ms] gpu gart end 0x%08X\n",
PCIE_R(PCIE_TX_GART_END_LO));
DRM_INFO("[radeon_ms] bus ready\n");
+ dev_priv->bus_ready = 1;
return 0;
}
{
struct drm_radeon_private *dev_priv = dev->dev_private;
+ if (!dev_priv->cp_ready) {
+ return 0;
+ }
dev_priv->cp_ready = 0;
radeon_ms_wait_for_idle(dev);
DRM_INFO("[radeon_ms] cp idle\n");
struct radeon_state *state = &dev_priv->driver_state;
int ret = 0;
+ dev_priv->cp_ready = -1;
if (dev_priv->microcode == NULL) {
DRM_INFO("[radeon_ms] no microcode not starting cp");
return 0;
return ret;
}
radeon_ms_gpu_restore(dev, &dev_priv->driver_state);
- dev_priv->bus_ready = 1;
/* initialize ttm */
ret = drm_bo_init_mm(dev, DRM_BO_MEM_TT, 0,
struct drm_radeon_private *dev_priv = dev->dev_private;
uint32_t fence_id, cmd[2], i, ret;
- if (!dev_priv || !dev_priv->cp_ready) {
+ if (!dev_priv || dev_priv->cp_ready != 1) {
return -EINVAL;
}
fence_id = (++dev_priv->fence_id_last);