drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10

on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk
deep sleep kicking in.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b7f5a94..f49f2d6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -326,7 +326,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
                                | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
                                | FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
                                | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
-                               | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
+                               | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
+                               | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
+                               | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
+                               | FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 
        if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)