* "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL,
+ DP_TRAINING_AUX_RD_INTERVAL,
(uint8_t *)&training_rd_interval,
sizeof(training_rd_interval));
{
core_link_write_dpcd(
link,
- DPCD_ADDRESS_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_SET,
&dpcd_pattern.raw,
1);
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x pattern = %x\n",
__func__,
- DPCD_ADDRESS_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_SET,
dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}
link_set_buffer[0] = rate;
link_set_buffer[1] = lane_count_set.raw;
- core_link_write_dpcd(link, DPCD_ADDRESS_LINK_BW_SET,
+ core_link_write_dpcd(link, DP_LINK_BW_SET,
link_set_buffer, 2);
- core_link_write_dpcd(link, DPCD_ADDRESS_DOWNSPREAD_CNTL,
+ core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
&downspread.raw, sizeof(downspread));
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
__func__,
- DPCD_ADDRESS_LINK_BW_SET,
+ DP_LINK_BW_SET,
lt_settings->link_settings.link_rate,
- DPCD_ADDRESS_LANE_COUNT_SET,
+ DP_LANE_COUNT_SET,
lt_settings->link_settings.lane_count,
- DPCD_ADDRESS_DOWNSPREAD_CNTL,
+ DP_DOWNSPREAD_CTRL,
lt_settings->link_settings.link_spread);
}
{
union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
const uint32_t dpcd_base_lt_offset =
- DPCD_ADDRESS_TRAINING_PATTERN_SET;
+ DP_TRAINING_PATTERN_SET;
uint8_t dpcd_lt_buffer[5] = {0};
union dpcd_training_pattern dpcd_pattern = {{0}};
uint32_t lane;
dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
hw_training_pattern_to_dpcd_training_pattern(link, pattern);
- dpcd_lt_buffer[DPCD_ADDRESS_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
+ dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
= dpcd_pattern.raw;
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x pattern = %x\n",
__func__,
- DPCD_ADDRESS_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_SET,
dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
/*****************************************************************
// 0x00103 - 0x00102
memmove(
- &dpcd_lt_buffer[DPCD_ADDRESS_LANE0_SET - dpcd_base_lt_offset],
+ &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
dpcd_lane,
size_in_bytes);
"%s:\n %x VS set = %x PE set = %x \
max VS Reached = %x max PE Reached = %x\n",
__func__,
- DPCD_ADDRESS_LANE0_SET,
+ DP_TRAINING_LANE0_SET,
dpcd_lane[0].bits.VOLTAGE_SWING_SET,
dpcd_lane[0].bits.PRE_EMPHASIS_SET,
dpcd_lane[0].bits.MAX_SWING_REACHED,
*/
core_link_write_dpcd(
link,
- DPCD_ADDRESS_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_SET,
&dpcd_pattern.raw,
sizeof(dpcd_pattern.raw) );
core_link_write_dpcd(
link,
- DPCD_ADDRESS_LANE0_SET,
+ DP_TRAINING_LANE0_SET,
(uint8_t *)(dpcd_lane),
size_in_bytes);
core_link_read_dpcd(
link,
- DPCD_ADDRESS_LANE_01_STATUS,
+ DP_LANE0_1_STATUS,
(uint8_t *)(dpcd_buf),
sizeof(dpcd_buf));
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
__func__,
- DPCD_ADDRESS_LANE_01_STATUS, dpcd_buf[0],
- DPCD_ADDRESS_LANE_23_STATUS, dpcd_buf[1]);
+ DP_LANE0_1_STATUS, dpcd_buf[0],
+ DP_LANE2_3_STATUS, dpcd_buf[1]);
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
__func__,
- DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1,
+ DP_ADJUST_REQUEST_LANE0_1,
dpcd_buf[4],
- DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3,
+ DP_ADJUST_REQUEST_LANE2_3,
dpcd_buf[5]);
/*copy to req_settings*/
}
core_link_write_dpcd(link,
- DPCD_ADDRESS_LANE0_SET,
+ DP_TRAINING_LANE0_SET,
(uint8_t *)(dpcd_lane),
link_training_setting->link_settings.lane_count);
"%s\n %x VS set = %x PE set = %x \
max VS Reached = %x max PE Reached = %x\n",
__func__,
- DPCD_ADDRESS_LANE0_SET,
+ DP_TRAINING_LANE0_SET,
dpcd_lane[0].bits.VOLTAGE_SWING_SET,
dpcd_lane[0].bits.PRE_EMPHASIS_SET,
dpcd_lane[0].bits.MAX_SWING_REACHED,
core_link_write_dpcd(
link,
- DPCD_ADDRESS_LANE_COUNT_SET,
+ DP_LANE_COUNT_SET,
&lane_count_set.raw,
sizeof(lane_count_set));
*/
dpcd_result = core_link_read_dpcd(link,
- DPCD_ADDRESS_POWER_STATE,
+ DP_SET_POWER,
&irq_reg_rx_power_state,
sizeof(irq_reg_rx_power_state));
if (dpcd_result != DC_OK) {
- irq_reg_rx_power_state = DP_PWR_STATE_D0;
+ irq_reg_rx_power_state = DP_SET_POWER_D0;
dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
"%s: DPCD read failed to obtain power state.\n",
__func__);
}
- if (irq_reg_rx_power_state == DP_PWR_STATE_D0) {
+ if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
/*2. Check that Link Status changed, before re-training.*/
*/
return core_link_read_dpcd(
link,
- DPCD_ADDRESS_SINK_COUNT,
+ DP_SINK_COUNT,
irq_data->raw,
sizeof(union hpd_irq_data));
}
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_LANE_COUNT,
+ DP_TEST_LANE_COUNT,
(unsigned char *)(&link_settings.lane_count),
1);
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_LINK_RATE,
+ DP_TEST_LINK_RATE,
(unsigned char *)(&link_settings.link_rate),
1);
union lane_adjust dpcd_lane_adjustment[2];
unsigned char dpcd_post_cursor_2_adjustment = 0;
unsigned char test_80_bit_pattern[
- (DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 -
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
+ (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
+ DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
enum dp_test_pattern test_pattern;
struct dc_link_training_settings link_settings;
union lane_adjust dpcd_lane_adjust;
/* get phy test pattern and pattern parameters from DP receiver */
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_PHY_PATTERN,
+ DP_TEST_PHY_PATTERN,
&dpcd_test_pattern.raw,
sizeof(dpcd_test_pattern));
core_link_read_dpcd(
link,
- DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1,
+ DP_ADJUST_REQUEST_LANE0_1,
&dpcd_lane_adjustment[0].raw,
sizeof(dpcd_lane_adjustment));
*/
core_link_read_dpcd(
link,
- DPCD_ADDRESS_ADJUST_REQUEST_POST_CURSOR2,
+ DP_ADJUST_REQUEST_POST_CURSOR2,
&dpcd_post_cursor_2_adjustment,
sizeof(dpcd_post_cursor_2_adjustment));
if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
test_80_bit_pattern,
sizeof(test_80_bit_pattern));
test_pattern,
&link_training_settings,
test_80_bit_pattern,
- (DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 -
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
+ (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
+ DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
}
static void dp_test_send_link_test_pattern(struct core_link *link)
/* get link test pattern and pattern parameters */
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_PATTERN,
+ DP_TEST_PATTERN,
&dpcd_test_pattern.raw,
sizeof(dpcd_test_pattern));
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_MISC1,
+ DP_TEST_MISC0,
&dpcd_test_params.raw,
sizeof(dpcd_test_params));
core_link_read_dpcd(
link,
- DPCD_ADDRESS_TEST_REQUEST,
+ DP_TEST_REQUEST,
&test_request.raw,
sizeof(union test_request));
if (test_request.bits.LINK_TRAINING) {
test_response.bits.ACK = 1;
core_link_write_dpcd(
link,
- DPCD_ADDRESS_TEST_RESPONSE,
+ DP_TEST_RESPONSE,
&test_response.raw,
sizeof(test_response));
dp_test_send_link_training(link);
if (test_response.bits.ACK)
core_link_write_dpcd(
link,
- DPCD_ADDRESS_TEST_RESPONSE,
+ DP_TEST_RESPONSE,
&test_response.raw,
sizeof(test_response));
}
device_service_clear.bits.AUTOMATED_TEST = 1;
core_link_write_dpcd(
link,
- DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR,
+ DP_DEVICE_SERVICE_IRQ_VECTOR,
&device_service_clear.raw,
sizeof(device_service_clear.raw));
device_service_clear.raw = 0;
rev.raw = 0;
cap.raw = 0;
- st = core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV, &rev.raw,
+ st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
sizeof(rev));
if (st == DC_OK && rev.raw >= DPCD_REV_12) {
- st = core_link_read_dpcd(link, DPCD_ADDRESS_MSTM_CAP,
+ st = core_link_read_dpcd(link, DP_MSTM_CAP,
&cap.raw, sizeof(cap));
if (st == DC_OK && cap.bits.MST_CAP == 1)
mst = true;
uint8_t det_caps[4];
union dwnstream_port_caps_byte0 *port_caps =
(union dwnstream_port_caps_byte0 *)det_caps;
- core_link_read_dpcd(link, DPCD_ADDRESS_DWN_STRM_PORT0_CAPS,
+ core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
det_caps, sizeof(det_caps));
switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
/* read IEEE branch device id */
core_link_read_dpcd(
link,
- DPCD_ADDRESS_BRANCH_DEVICE_ID_START,
+ DP_BRANCH_OUI,
(uint8_t *)&dp_id,
sizeof(dp_id));
core_link_read_dpcd(
link,
- DPCD_ADDRESS_BRANCH_REVISION_START,
+ DP_BRANCH_REVISION_START,
(uint8_t *)&dp_hw_fw_revision,
sizeof(dp_hw_fw_revision));
if (!link->dpcd_caps.dpcd_rev.raw) {
do {
dp_receiver_power_ctrl(link, true);
- core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV,
+ core_link_read_dpcd(link, DP_DPCD_REV,
dpcd_data, length);
link->dpcd_caps.dpcd_rev.raw = dpcd_data[
- DPCD_ADDRESS_DPCD_REV -
- DPCD_ADDRESS_DPCD_REV];
+ DP_DPCD_REV -
+ DP_DPCD_REV];
} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
}
- ds_port.byte = dpcd_data[DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT -
- DPCD_ADDRESS_DPCD_REV];
+ ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
+ DP_DPCD_REV];
if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
switch (link->dpcd_caps.branch_dev_id) {
{
if (edp_revision >= EDP_REVISION_13) {
core_link_read_dpcd(link,
- DPCD_ADDRESS_PSR_SUPPORT_VER,
+ DP_PSR_SUPPORT,
(uint8_t *)(&link->public.psr_caps),
sizeof(link->public.psr_caps));
if (link->public.psr_caps.psr_version != 0) {
unsigned char psr_capability = 0;
core_link_read_dpcd(link,
- DPCD_ADDRESS_PSR_CAPABILITY,
+ DP_PSR_CAPS,
&psr_capability,
sizeof(psr_capability));
/* Bit 0 determines whether fast link training is
static void retrieve_link_cap(struct core_link *link)
{
- uint8_t dpcd_data[DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL - DPCD_ADDRESS_DPCD_REV + 1];
+ uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
union down_stream_port_count down_strm_port_count;
union edp_configuration_cap edp_config_cap;
core_link_read_dpcd(
link,
- DPCD_ADDRESS_DPCD_REV,
+ DP_DPCD_REV,
dpcd_data,
sizeof(dpcd_data));
link->dpcd_caps.dpcd_rev.raw =
- dpcd_data[DPCD_ADDRESS_DPCD_REV - DPCD_ADDRESS_DPCD_REV];
+ dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
{
union training_aux_rd_interval aux_rd_interval;
aux_rd_interval.raw =
- dpcd_data[DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL];
+ dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
core_link_read_dpcd(
link,
- DPCD_ADDRESS_DP13_DPCD_REV,
+ DP_DP13_DPCD_REV,
dpcd_data,
sizeof(dpcd_data));
}
}
- ds_port.byte = dpcd_data[DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT -
- DPCD_ADDRESS_DPCD_REV];
+ ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
+ DP_DPCD_REV];
get_active_converter_info(ds_port.byte, link);
down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
link->dpcd_caps.max_ln_count.raw = dpcd_data[
- DPCD_ADDRESS_MAX_LANE_COUNT - DPCD_ADDRESS_DPCD_REV];
+ DP_MAX_LANE_COUNT - DP_DPCD_REV];
link->dpcd_caps.max_down_spread.raw = dpcd_data[
- DPCD_ADDRESS_MAX_DOWNSPREAD - DPCD_ADDRESS_DPCD_REV];
+ DP_MAX_DOWNSPREAD - DP_DPCD_REV];
link->public.reported_link_cap.lane_count =
link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
link->public.reported_link_cap.link_rate = dpcd_data[
- DPCD_ADDRESS_MAX_LINK_RATE - DPCD_ADDRESS_DPCD_REV];
+ DP_MAX_LINK_RATE - DP_DPCD_REV];
link->public.reported_link_cap.link_spread =
link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
edp_config_cap.raw = dpcd_data[
- DPCD_ADDRESS_EDP_CONFIG_CAP - DPCD_ADDRESS_DPCD_REV];
+ DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
link->dpcd_caps.panel_mode_edp =
edp_config_cap.bits.ALT_SCRAMBLER_RESET;
/* read sink count */
core_link_read_dpcd(link,
- DPCD_ADDRESS_SINK_COUNT,
+ DP_SINK_COUNT,
&link->dpcd_caps.sink_count.raw,
sizeof(link->dpcd_caps.sink_count.raw));
if (edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE) {
/* Read the Panel's eDP revision at DPCD 700h. */
core_link_read_dpcd(link,
- DPCD_ADDRESS_EDP_REV,
+ DP_EDP_DPCD_REV,
(uint8_t *)(&link->edp_revision),
sizeof(link->edp_revision));
}
(unsigned char)(pattern);
core_link_write_dpcd(core_link,
- DPCD_ADDRESS_LINK_QUAL_LANE0_SET,
+ DP_LINK_QUAL_LANE0_SET,
link_qual_pattern,
sizeof(link_qual_pattern));
} else if (core_link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
* setting test pattern for DP 1.1.
*/
core_link_read_dpcd(core_link,
- DPCD_ADDRESS_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_SET,
&training_pattern.raw,
sizeof(training_pattern));
training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
core_link_write_dpcd(core_link,
- DPCD_ADDRESS_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_SET,
&training_pattern.raw,
sizeof(training_pattern));
}
SET_TEST_PATTERN_PENDING = 0;
test_response.bits.ACK = 1;
core_link_write_dpcd(core_link,
- DPCD_ADDRESS_TEST_RESPONSE,
+ DP_TEST_RESPONSE,
&test_response.raw,
sizeof(test_response));
}
#ifndef __DAL_DPCD_DEFS_H__
#define __DAL_DPCD_DEFS_H__
-enum dpcd_address {
-/* addresses marked with 1.2 are only defined since DP 1.2 spec */
-
- /* Reciever Capability Field */
- DPCD_ADDRESS_DPCD_REV = 0x00000,
- DPCD_ADDRESS_MAX_LINK_RATE = 0x00001,
- DPCD_ADDRESS_MAX_LANE_COUNT = 0x00002,
- DPCD_ADDRESS_MAX_DOWNSPREAD = 0x00003,
- DPCD_ADDRESS_NORP = 0x00004,
- DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT = 0x00005,
- DPCD_ADDRESS_MAIN_LINK_CHANNEL_CODING = 0x00006,
- DPCD_ADDRESS_DOWNSTREAM_PORT_COUNT = 0x00007,
- DPCD_ADDRESS_RECEIVE_PORT0_CAP0 = 0x00008,
- DPCD_ADDRESS_RECEIVE_PORT0_CAP1 = 0x00009,
- DPCD_ADDRESS_RECEIVE_PORT1_CAP0 = 0x0000A,
- DPCD_ADDRESS_RECEIVE_PORT1_CAP1 = 0x0000B,
-
- DPCD_ADDRESS_I2C_SPEED_CNTL_CAP = 0x0000C,/*1.2*/
- DPCD_ADDRESS_EDP_CONFIG_CAP = 0x0000D,/*1.2*/
- DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL = 0x000E,/*1.2*/
-
- DPCD_ADDRESS_MSTM_CAP = 0x00021,/*1.2*/
-
- /* Audio Video Sync Data Feild */
- DPCD_ADDRESS_AV_GRANULARITY = 0x0023,
- DPCD_ADDRESS_AUDIO_DECODE_LATENCY1 = 0x0024,
- DPCD_ADDRESS_AUDIO_DECODE_LATENCY2 = 0x0025,
- DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY1 = 0x0026,
- DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY2 = 0x0027,
- DPCD_ADDRESS_VIDEO_INTERLACED_LATENCY = 0x0028,
- DPCD_ADDRESS_VIDEO_PROGRESSIVE_LATENCY = 0x0029,
- DPCD_ADDRESS_AUDIO_DELAY_INSERT1 = 0x0002B,
- DPCD_ADDRESS_AUDIO_DELAY_INSERT2 = 0x0002C,
- DPCD_ADDRESS_AUDIO_DELAY_INSERT3 = 0x0002D,
-
- /* Audio capability */
- DPCD_ADDRESS_NUM_OF_AUDIO_ENDPOINTS = 0x00022,
-
- DPCD_ADDRESS_GUID_START = 0x00030,/*1.2*/
- DPCD_ADDRESS_GUID_END = 0x0003f,/*1.2*/
-
- DPCD_ADDRESS_PSR_SUPPORT_VER = 0x00070,
- DPCD_ADDRESS_PSR_CAPABILITY = 0x00071,
-
- DPCD_ADDRESS_DWN_STRM_PORT0_CAPS = 0x00080,/*1.2a*/
-
- /* Link Configuration Field */
- DPCD_ADDRESS_LINK_BW_SET = 0x00100,
- DPCD_ADDRESS_LANE_COUNT_SET = 0x00101,
- DPCD_ADDRESS_TRAINING_PATTERN_SET = 0x00102,
- DPCD_ADDRESS_LANE0_SET = 0x00103,
- DPCD_ADDRESS_LANE1_SET = 0x00104,
- DPCD_ADDRESS_LANE2_SET = 0x00105,
- DPCD_ADDRESS_LANE3_SET = 0x00106,
- DPCD_ADDRESS_DOWNSPREAD_CNTL = 0x00107,
- DPCD_ADDRESS_I2C_SPEED_CNTL = 0x00109,/*1.2*/
-
- DPCD_ADDRESS_EDP_CONFIG_SET = 0x0010A,
- DPCD_ADDRESS_LINK_QUAL_LANE0_SET = 0x0010B,
- DPCD_ADDRESS_LINK_QUAL_LANE1_SET = 0x0010C,
- DPCD_ADDRESS_LINK_QUAL_LANE2_SET = 0x0010D,
- DPCD_ADDRESS_LINK_QUAL_LANE3_SET = 0x0010E,
-
- DPCD_ADDRESS_LANE0_SET2 = 0x0010F,/*1.2*/
- DPCD_ADDRESS_LANE2_SET2 = 0x00110,/*1.2*/
-
- DPCD_ADDRESS_MSTM_CNTL = 0x00111,/*1.2*/
-
- DPCD_ADDRESS_PSR_ENABLE_CFG = 0x0170,
-
- /* Payload Table Configuration Field 1.2 */
- DPCD_ADDRESS_PAYLOAD_ALLOCATE_SET = 0x001C0,
- DPCD_ADDRESS_PAYLOAD_ALLOCATE_START_TIMESLOT = 0x001C1,
- DPCD_ADDRESS_PAYLOAD_ALLOCATE_TIMESLOT_COUNT = 0x001C2,
-
- DPCD_ADDRESS_SINK_COUNT = 0x0200,
- DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR = 0x0201,
-
- /* Link / Sink Status Field */
- DPCD_ADDRESS_LANE_01_STATUS = 0x00202,
- DPCD_ADDRESS_LANE_23_STATUS = 0x00203,
- DPCD_ADDRESS_LANE_ALIGN_STATUS_UPDATED = 0x0204,
- DPCD_ADDRESS_SINK_STATUS = 0x0205,
-
- /* Adjust Request Field */
- DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1 = 0x0206,
- DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3 = 0x0207,
- DPCD_ADDRESS_ADJUST_REQUEST_POST_CURSOR2 = 0x020C,
-
- /* Test Request Field */
- DPCD_ADDRESS_TEST_REQUEST = 0x0218,
- DPCD_ADDRESS_TEST_LINK_RATE = 0x0219,
- DPCD_ADDRESS_TEST_LANE_COUNT = 0x0220,
- DPCD_ADDRESS_TEST_PATTERN = 0x0221,
- DPCD_ADDRESS_TEST_MISC1 = 0x0232,
-
- /* Phy Test Pattern Field */
- DPCD_ADDRESS_TEST_PHY_PATTERN = 0x0248,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0 = 0x0250,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_15_8 = 0x0251,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_23_16 = 0x0252,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_31_24 = 0x0253,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_39_32 = 0x0254,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_47_40 = 0x0255,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_55_48 = 0x0256,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_63_56 = 0x0257,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_71_64 = 0x0258,
- DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 = 0x0259,
-
- /* Test Response Field*/
- DPCD_ADDRESS_TEST_RESPONSE = 0x0260,
-
- /* Audio Test Pattern Field 1.2*/
- DPCD_ADDRESS_TEST_AUDIO_MODE = 0x0271,
- DPCD_ADDRESS_TEST_AUDIO_PATTERN_TYPE = 0x0272,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_1 = 0x0273,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_2 = 0x0274,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_3 = 0x0275,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_4 = 0x0276,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_5 = 0x0277,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_6 = 0x0278,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_7 = 0x0279,
- DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_8 = 0x027A,
-
- /* Payload Table Status Field */
- DPCD_ADDRESS_PAYLOAD_TABLE_UPDATE_STATUS = 0x002C0,/*1.2*/
- DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT1 = 0x002C1,/*1.2*/
- DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT63 = 0x002FF,/*1.2*/
-
- /* Source Device Specific Field */
- DPCD_ADDRESS_SOURCE_DEVICE_ID_START = 0x0300,
- DPCD_ADDRESS_SOURCE_DEVICE_ID_END = 0x0301,
- DPCD_ADDRESS_AMD_INTERNAL_DEBUG_START = 0x030C,
- DPCD_ADDRESS_AMD_INTERNAL_DEBUG_END = 0x030F,
- DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_START = 0x0310,
- DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_END = 0x037F,
- DPCD_ADDRESS_SOURCE_RESERVED_START = 0x0380,
- DPCD_ADDRESS_SOURCE_RESERVED_END = 0x03FF,
-
- /* Sink Device Specific Field */
- DPCD_ADDRESS_SINK_DEVICE_ID_START = 0x0400,
- DPCD_ADDRESS_SINK_DEVICE_ID_END = 0x0402,
- DPCD_ADDRESS_SINK_DEVICE_STR_START = 0x0403,
- DPCD_ADDRESS_SINK_DEVICE_STR_END = 0x0408,
- DPCD_ADDRESS_SINK_REVISION_START = 0x409,
- DPCD_ADDRESS_SINK_REVISION_END = 0x40B,
-
- /* Branch Device Specific Field */
- DPCD_ADDRESS_BRANCH_DEVICE_ID_START = 0x0500,
- DPCD_ADDRESS_BRANCH_DEVICE_ID_END = 0x0502,
- DPCD_ADDRESS_BRANCH_DEVICE_STR_START = 0x0503,
- DPCD_ADDRESS_BRANCH_DEVICE_STR_END = 0x0508,
- DPCD_ADDRESS_BRANCH_REVISION_START = 0x0509,
- DPCD_ADDRESS_BRANCH_REVISION_END = 0x050B,
-
- DPCD_ADDRESS_POWER_STATE = 0x0600,
-
- /* EDP related */
- DPCD_ADDRESS_EDP_REV = 0x0700,
- DPCD_ADDRESS_EDP_CAPABILITY = 0x0701,
- DPCD_ADDRESS_EDP_BACKLIGHT_ADJUST_CAP = 0x0702,
- DPCD_ADDRESS_EDP_GENERAL_CAP2 = 0x0703,
-
- DPCD_ADDRESS_EDP_DISPLAY_CONTROL = 0x0720,
- DPCD_ADDRESS_SUPPORTED_LINK_RATES = 0x00010, /* edp 1.4 */
- DPCD_ADDRESS_EDP_BACKLIGHT_SET = 0x0721,
- DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_MSB = 0x0722,
- DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_LSB = 0x0723,
- DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT = 0x0724,
- DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MIN = 0x0725,
- DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MAX = 0x0726,
- DPCD_ADDRESS_EDP_BACKLIGHT_CONTROL_STATUS = 0x0727,
- DPCD_ADDRESS_EDP_BACKLIGHT_FREQ_SET = 0x0728,
- DPCD_ADDRESS_EDP_REVERVED = 0x0729,
- DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MSB = 0x072A,
- DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MID = 0x072B,
- DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_LSB = 0x072C,
- DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MSB = 0x072D,
- DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MID = 0x072E,
- DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_LSB = 0x072F,
-
- DPCD_ADDRESS_EDP_DBC_MINIMUM_BRIGHTNESS_SET = 0x0732,
- DPCD_ADDRESS_EDP_DBC_MAXIMUM_BRIGHTNESS_SET = 0x0733,
-
- /* Sideband MSG Buffers 1.2 */
- DPCD_ADDRESS_DOWN_REQ_START = 0x01000,
- DPCD_ADDRESS_DOWN_REQ_END = 0x011ff,
-
- DPCD_ADDRESS_UP_REP_START = 0x01200,
- DPCD_ADDRESS_UP_REP_END = 0x013ff,
-
- DPCD_ADDRESS_DOWN_REP_START = 0x01400,
- DPCD_ADDRESS_DOWN_REP_END = 0x015ff,
-
- DPCD_ADDRESS_UP_REQ_START = 0x01600,
- DPCD_ADDRESS_UP_REQ_END = 0x017ff,
-
- /* ESI (Event Status Indicator) Field 1.2 */
- DPCD_ADDRESS_SINK_COUNT_ESI = 0x02002,
- DPCD_ADDRESS_DEVICE_IRQ_ESI0 = 0x02003,
- DPCD_ADDRESS_DEVICE_IRQ_ESI1 = 0x02004,
- /*@todo move dpcd_address_Lane01Status back here*/
-
- DPCD_ADDRESS_PSR_ERROR_STATUS = 0x2006,
- DPCD_ADDRESS_PSR_EVENT_STATUS = 0x2007,
- DPCD_ADDRESS_PSR_SINK_STATUS = 0x2008,
- DPCD_ADDRESS_PSR_DBG_REGISTER0 = 0x2009,
- DPCD_ADDRESS_PSR_DBG_REGISTER1 = 0x200A,
-
- DPCD_ADDRESS_DP13_DPCD_REV = 0x2200,
- DPCD_ADDRESS_DP13_MAX_LINK_RATE = 0x2201,
-
- /* Travis specific addresses */
- DPCD_ADDRESS_TRAVIS_SINK_DEV_SEL = 0x5f0,
- DPCD_ADDRESS_TRAVIS_SINK_ACCESS_OFFSET = 0x5f1,
- DPCD_ADDRESS_TRAVIS_SINK_ACCESS_REG = 0x5f2,
-};
+#include <drm/drm_dp_helper.h>
enum dpcd_revision {
DPCD_REV_10 = 0x10,
DPCD_REV_14 = 0x14
};
-enum dp_pwr_state {
- DP_PWR_STATE_D0 = 1,/* direct HW translation! */
- DP_PWR_STATE_D3
-};
-
/* these are the types stored at DOWNSTREAMPORT_PRESENT */
enum dpcd_downstream_port_type {
DOWNSTREAM_DP = 0,
projects / platform / kernel / linux-starfive.git / commitdiff