Change-Id: I56a6db438004ddd2d1906df9b718846bd8adbf91
* This enters S0i3, C6 or C4 depending on what is currently permitted.
* C1-C4 are handled via the normal intel_idle entry.
*/
+extern void do_s0i3(void);
+
int intel_mid_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
{
unsigned long ecx = 1; /* break on interrupt flag */
if (!need_resched()) {
#ifdef CONFIG_X86_MRST
if (eax == -1UL) {
- do_s0i3();
+ ;//do_s0i3();
} else
#endif
{
#include <asm/mwait.h>
#include <asm/mrst.h>
-static void do_s0i3(void);
+void do_s0i3(void);
static u64 *wakeup_ptr;
static phys_addr_t s0i3_trampoline_phys;
static void *s0i3_trampoline_base;
*wakeup_ptr = virt_to_phys(mrst_s0i3_resume);
}
-static noinline void do_s0i3(void)
+noinline void do_s0i3(void)
{
s0i3_update_wake_pointer();
mrst_pmu_disable_msi(); /* disable MSIs before save LAPIC */