aarch64: Fix several *<LOGICAL:optab>_ashl<mode>3 related regressions [PR100056]

Before combiner added 2 to 2 combinations, the following testcase functions
have been all compiled into 2 instructions, zero/sign extensions or and
followed by orr with lsl, e.g. for the first function
Trying 7 -> 8:
    7: r96:SI=r94:SI<<0xb
    8: r95:SI=r96:SI|r94:SI
      REG_DEAD r96:SI
      REG_DEAD r94:SI
Successfully matched this instruction:
(set (reg:SI 95)
    (ior:SI (ashift:SI (reg/v:SI 94 [ i ])
            (const_int 11 [0xb]))
        (reg/v:SI 94 [ i ])))
is the important successful try_combine and so we end up with
        and     w0, w0, 255
        orr     w0, w0, w0, lsl 11
in the body.
With 2 to 2 combination, before that can trigger, another successful
combination:
Trying 2 -> 7:
    2: r94:SI=zero_extend(x0:QI)
      REG_DEAD x0:QI
    7: r96:SI=r94:SI<<0xb
is replaced with:
(set (reg/v:SI 94 [ i ])
    (zero_extend:SI (reg:QI 0 x0 [ i ])))
and
(set (reg:SI 96)
    (and:SI (ashift:SI (reg:SI 0 x0 [ i ])
            (const_int 11 [0xb]))
        (const_int 522240 [0x7f800])))
and in the end results in 3 instructions in the body:
        and     w1, w0, 255
        ubfiz   w0, w0, 11, 8
        orr     w0, w0, w1
The following combine splitters help undo that when combiner tries to
combine 3 instructions - the zero/sign extend or and, the other insn
from the 2 to 2 combination ([us]bfiz) and the logical op, the CPUs
don't have an insn to do everything in one op, but we can split it
back into the zero/sign extend or and followed by logical with lsl.

2021-04-15  Jakub Jelinek  <jakub@redhat.com>

	PR target/100056
	* config/aarch64/aarch64.md (*<LOGICAL:optab>_<SHIFT:optab><mode>3):
	Add combine splitters for *<LOGICAL:optab>_ashl<mode>3 with
	ZERO_EXTEND, SIGN_EXTEND or AND.

	* gcc.target/aarch64/pr100056.c: New test.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 9a7ed78..962640b 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4431,6 +4431,59 @@
   [(set_attr "type" "logic_shift_imm")]
 )
 
+(define_split
+  [(set (match_operand:GPI 0 "register_operand")
+       (LOGICAL:GPI
+         (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand")
+                              (match_operand:QI 2 "aarch64_shift_imm_<mode>"))
+                  (match_operand:GPI 3 "const_int_operand"))
+         (zero_extend:GPI (match_operand 4 "register_operand"))))]
+  "can_create_pseudo_p ()
+   && ((paradoxical_subreg_p (operands[1])
+       && rtx_equal_p (SUBREG_REG (operands[1]), operands[4]))
+       || (REG_P (operands[1])
+          && REG_P (operands[4])
+          && REGNO (operands[1]) == REGNO (operands[4])))
+   && (trunc_int_for_mode (GET_MODE_MASK (GET_MODE (operands[4]))
+                          << INTVAL (operands[2]), <MODE>mode)
+       == INTVAL (operands[3]))"
+  [(set (match_dup 5) (zero_extend:GPI (match_dup 4)))
+   (set (match_dup 0) (LOGICAL:GPI (ashift:GPI (match_dup 5) (match_dup 2))
+                                  (match_dup 5)))]
+  "operands[5] = gen_reg_rtx (<MODE>mode);"
+)
+
+(define_split
+  [(set (match_operand:GPI 0 "register_operand")
+       (LOGICAL:GPI
+         (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand")
+                              (match_operand:QI 2 "aarch64_shift_imm_<mode>"))
+                  (match_operand:GPI 4 "const_int_operand"))
+         (and:GPI (match_dup 1) (match_operand:GPI 3 "const_int_operand"))))]
+  "can_create_pseudo_p ()
+   && pow2_or_zerop (UINTVAL (operands[3]) + 1)
+   && (trunc_int_for_mode (UINTVAL (operands[3])
+                          << INTVAL (operands[2]), <MODE>mode)
+       == INTVAL (operands[4]))"
+  [(set (match_dup 5) (and:GPI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (LOGICAL:GPI (ashift:GPI (match_dup 5) (match_dup 2))
+                                  (match_dup 5)))]
+  "operands[5] = gen_reg_rtx (<MODE>mode);"
+)
+
+(define_split
+  [(set (match_operand:GPI 0 "register_operand")
+       (LOGICAL:GPI
+         (ashift:GPI (sign_extend:GPI (match_operand 1 "register_operand"))
+                     (match_operand:QI 2 "aarch64_shift_imm_<mode>"))
+         (sign_extend:GPI (match_dup 1))))]
+  "can_create_pseudo_p ()"
+  [(set (match_dup 3) (sign_extend:GPI (match_dup 1)))
+   (set (match_dup 0) (LOGICAL:GPI (ashift:GPI (match_dup 3) (match_dup 2))
+                                  (match_dup 3)))]
+  "operands[3] = gen_reg_rtx (<MODE>mode);"
+)
+
 (define_insn "*<optab>_rol<mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (LOGICAL:GPI (rotate:GPI

diff --git a/gcc/testsuite/gcc.target/aarch64/pr100056.c b/gcc/testsuite/gcc.target/aarch64/pr100056.c
new file mode 100644 (file)
index 0000000..0b77824
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr100056.c
@@ -0,0 +1,58 @@
+/* PR target/100056 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not {\t[us]bfiz\tw[0-9]+, w[0-9]+, 11} } } */
+
+int
+or_shift_u8 (unsigned char i)
+{
+  return i | (i << 11);
+}
+
+int
+or_shift_u3a (unsigned i)
+{
+  i &= 7;
+  return i | (i << 11);
+}
+
+int
+or_shift_u3b (unsigned i)
+{
+  i = (i << 29) >> 29;
+  return i | (i << 11);
+}
+
+int
+or_shift_s16 (signed short i)
+{
+  return i | (i << 11);
+}
+
+int
+or_shift_s8 (signed char i)
+{
+  return i | (i << 11);
+}
+
+int
+or_shift_s13 (int i)
+{
+  i = (i << 19) >> 19;
+  return i | (i << 11);
+}
+
+int
+or_shift_s3 (int i)
+{
+  i = (i << 29) >> 29;
+  return i | (i << 11);
+}
+
+int
+or_shift_u8_asm (unsigned char x)
+{
+  unsigned char i = x;
+  asm volatile ("" : "+r" (i));
+  return i | (i << 11);
+}