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arm: zynq: dt: Set correct L2 ram latencies
author
Soren Brinkmann
<soren.brinkmann@xilinx.com>
Wed, 31 Jul 2013 23:24:59 +0000
(16:24 -0700)
committer
Michal Simek
<michal.simek@xilinx.com>
Tue, 13 Aug 2013 14:37:35 +0000
(16:37 +0200)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/boot/dts/zynq-7000.dtsi
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diff --git
a/arch/arm/boot/dts/zynq-7000.dtsi
b/arch/arm/boot/dts/zynq-7000.dtsi
index
6f54a64
..
e32b92b
100644
(file)
--- a/
arch/arm/boot/dts/zynq-7000.dtsi
+++ b/
arch/arm/boot/dts/zynq-7000.dtsi
@@
-41,8
+41,8
@@
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
- arm,data-latency = <
2 3
2>;
- arm,tag-latency = <2
3
2>;
+ arm,data-latency = <
3 2
2>;
+ arm,tag-latency = <2
2
2>;
cache-unified;
cache-level = <2>;
};