radv: use correct VGT_TESS_DISTRIBUTION settings on GFX11
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Mon, 17 Oct 2022 08:20:30 +0000 (08:20 +0000)
committerMarge Bot <emma+marge@anholt.net>
Thu, 20 Oct 2022 08:55:04 +0000 (08:55 +0000)
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19155>

src/amd/vulkan/si_cmd_buffer.c

index 565e22d..5c5140f 100644 (file)
@@ -504,7 +504,13 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
       }
    }
 
-   if (physical_device->rad_info.gfx_level >= GFX9) {
+   if (physical_device->rad_info.gfx_level >= GFX11) {
+      /* ACCUM fields changed their meaning. */
+      radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
+                                 S_028B50_ACCUM_ISOLINE(255) | S_028B50_ACCUM_TRI(255) |
+                                 S_028B50_ACCUM_QUAD(255) | S_028B50_DONUT_SPLIT_GFX9(24) |
+                                 S_028B50_TRAP_SPLIT(6));
+   } else if (physical_device->rad_info.gfx_level >= GFX9) {
       radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
                              S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) |
                                 S_028B50_ACCUM_QUAD(24) | S_028B50_DONUT_SPLIT_GFX9(24) |