* rs6000.h (GO_IF_LEGITIMATE_ADDRESS): Use TARGET_POWERPC64

        when testing LEGITIMATE_INDEXED_ADDRESS_P DFmode and DImode.
        (LEGITIMIZE_ADDRESS): Use TARGET_POWERPC64 for INDEXED fixup.
        * rs6000.c (print_operand, case 'L'): Add UNITS_PER_WORD, not 4.
        (print_operand, cases 'O' and 'T'): Fix typos in lossage strings.
        * rs6000.md (fix_truncdfsi2_store): Remove %w from non-CONST_INT
        operand.
        (movdf_softfloat32, movdf_hardfloat64, movdf_softfloat64): Change
        'o' to 'm' for GPR variant constraints.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@21947 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4327d04..d7eaad5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+Mon Aug 24 15:20:19 1998  David Edelsohn  <edelsohn@mhpcc.edu>
+
+       * rs6000.h (GO_IF_LEGITIMATE_ADDRESS): Use TARGET_POWERPC64
+       when testing LEGITIMATE_INDEXED_ADDRESS_P DFmode and DImode.
+       (LEGITIMIZE_ADDRESS): Use TARGET_POWERPC64 for INDEXED fixup.
+       * rs6000.c (print_operand, case 'L'): Add UNITS_PER_WORD, not 4.
+       (print_operand, cases 'O' and 'T'): Fix typos in lossage strings.
+       * rs6000.md (fix_truncdfsi2_store): Remove %w from non-CONST_INT
+       operand. 
+       (movdf_softfloat32, movdf_hardfloat64, movdf_softfloat64): Change
+       'o' to 'm' for GPR variant constraints.
+
 Mon Aug 24 10:25:46 1998  Jeffrey A Law  (law@cygnus.com)
 
         * loop.c (scan_loop): Honor AVOID_CC_MODE_COPIES.

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5d85bac..022e3cf 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2187,7 +2187,7 @@ secondary_reload_class (class, mode, in)
   if (regno >= FIRST_PSEUDO_REGISTER)
     regno = -1;
 
-  /* We can not copy a symbolic operand directly into anyting other than
+  /* We can not copy a symbolic operand directly into anything other than
      BASE_REGS for TARGET_ELF.  So indicate that a register from BASE_REGS
      is needed as an intermediate register.  */
   if (TARGET_ELF
@@ -2695,12 +2695,13 @@ print_operand (file, x, code)
       else if (GET_CODE (x) == MEM)
        {
          /* Handle possible auto-increment.  Since it is pre-increment and
-            we have already done it, we can just use an offset of four.  */
+            we have already done it, we can just use an offset of word.  */
          if (GET_CODE (XEXP (x, 0)) == PRE_INC
              || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-           output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
+           output_address (plus_constant (XEXP (XEXP (x, 0), 0),
+                                          UNITS_PER_WORD));
          else
-           output_address (plus_constant (XEXP (x, 0), 4));
+           output_address (plus_constant (XEXP (x, 0), UNITS_PER_WORD));
          if (small_data_operand (x, GET_MODE (x)))
            fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
                     reg_names[SMALL_DATA_REG]);
@@ -2789,7 +2790,7 @@ print_operand (file, x, code)
     case 'O':
       /* Similar, but subtract 1 first.  */
       if (GET_CODE (x) != PARALLEL)
-       output_operand_lossage ("invalid %%N value");
+       output_operand_lossage ("invalid %%O value");
 
       fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
       return;
@@ -2912,7 +2913,7 @@ print_operand (file, x, code)
       /* Opposite of 't': write 4 if this jump operation will branch if true,
         12 otherwise.   */
       if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-       output_operand_lossage ("invalid %%t value");
+       output_operand_lossage ("invalid %%T value");
 
       else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
                && GET_CODE (x) != NE)

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ae38d99..3d9e701 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -716,7 +716,7 @@ extern int rs6000_debug_arg;                /* debug argument handling */
        mq              (not saved; best to use it if we can)
        ctr             (not saved; when we have the choice ctr is better)
        lr              (saved)
-        cr5, r1, r2, ap        (fixed)  */
+        cr5, r1, r2, ap, fpmem (fixed)  */
 
 #define REG_ALLOC_ORDER                                        \
   {32,                                                         \
@@ -1798,7 +1798,12 @@ typedef struct rs6000_args
    the sum of two registers, or a register indirect, possibly with an
    auto-increment.  For DFmode and DImode with an constant plus register,
    we must ensure that both words are addressable or PowerPC64 with offset
-   word aligned.  */
+   word aligned.
+
+   For modes spanning multiple registers (DFmode in 32-bit GPRs,
+   32-bit DImode, TImode), indexed addressing cannot be used because
+   adjacent memory cells are accessed by adding word-sized offsets
+   during assembly output.  */
 
 #define LEGITIMATE_CONSTANT_POOL_BASE_P(X)                             \
   (TARGET_TOC && GET_CODE (X) == SYMBOL_REF                            \
@@ -1875,8 +1880,8 @@ typedef struct rs6000_args
   if (LEGITIMATE_OFFSET_ADDRESS_P (MODE, X))           \
     goto ADDR;                                         \
   if ((MODE) != TImode                                 \
-      && (TARGET_HARD_FLOAT || TARGET_64BIT || (MODE) != DFmode) \
-      && (TARGET_64BIT || (MODE) != DImode)            \
+      && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || (MODE) != DFmode) \
+      && (TARGET_POWERPC64 || (MODE) != DImode)                \
       && LEGITIMATE_INDEXED_ADDRESS_P (X))             \
     goto ADDR;                                         \
   if (LEGITIMATE_LO_SUM_ADDRESS_P (MODE, X))           \
@@ -1923,8 +1928,8 @@ typedef struct rs6000_args
     }                                                                  \
   else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG       \
           && GET_CODE (XEXP (X, 1)) != CONST_INT                       \
-          && (TARGET_HARD_FLOAT || TARGET_64BIT || (MODE) != DFmode)   \
-          && (TARGET_64BIT || (MODE) != DImode)                        \
+          && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || (MODE) != DFmode) \
+          && (TARGET_POWERPC64 || (MODE) != DImode)                    \
           && (MODE) != TImode)                                         \
     {                                                                  \
       (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),                          \

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 22b587c..65af962 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3892,7 +3892,7 @@
                                  GEN_INT ((((rs6000_fpmem_offset & 0xffff)
                                             ^ 0x8000) - 0x8000))));
 
-  return \"stfd %0,%w2\";
+  return \"stfd %0,%2\";
 }"
   [(set_attr "type" "fpstore")])
 
@@ -5942,7 +5942,7 @@
 }")
 
 ;; Don't have reload use general registers to load a constant.  First,
-;; it might not work if the output operand has is the equivalent of
+;; it might not work if the output operand is the equivalent of
 ;; a non-offsettable memref, but also it is less efficient than loading
 ;; the constant into an FP register, since it will probably be used there.
 ;; The "??" is a kludge until we can figure out a more reasonable way
@@ -5995,8 +5995,8 @@
    (set_attr "length" "8,8,8,8,12,16,*,*,*")])
 
 (define_insn "*movdf_softfloat32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
-       (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
+       (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
   "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode))"
@@ -6036,8 +6036,8 @@
    (set_attr "length" "8,8,8,8,12,16")])
 
 (define_insn "*movdf_hardfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
-       (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
+       (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode))"
@@ -6055,8 +6055,8 @@
    (set_attr "length" "4,4,4,8,12,16,4,4,4")])
 
 (define_insn "*movdf_softfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
-       (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
+       (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
   "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode))"