};
a57_1: cpu@1 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
};
a57_2: cpu@2 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x2>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
};
a57_3: cpu@3 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x3>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
};
a53_1: cpu@101 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
};
a53_2: cpu@102 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
};
a53_3: cpu@103 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,