[ARM64] Fix UnspillReg instruction generation

Fixes the runtime issues (#16359,#15389) seen with COMPlus_JitStressRegs=0x2* on ARM64.

diff --git a/src/jit/codegenlinear.cpp b/src/jit/codegenlinear.cpp
index eddec19..6faaf61 100644 (file)
--- a/src/jit/codegenlinear.cpp
+++ b/src/jit/codegenlinear.cpp
@@ -896,10 +896,15 @@ void CodeGen::genUnspillRegIfNeeded(GenTree* tree)
                 inst_RV_TT(ins_Load(treeType, compiler->isSIMDTypeLocalAligned(lcl->gtLclNum)), dstReg, unspillTree);
             }
 #elif defined(_TARGET_ARM64_)
-            var_types   targetType = unspillTree->gtType;
-            instruction ins        = ins_Load(targetType, compiler->isSIMDTypeLocalAligned(lcl->gtLclNum));
-            emitAttr    attr       = emitTypeSize(targetType);
-            emitter*    emit       = getEmitter();
+            var_types targetType = unspillTree->gtType;
+            if (targetType != genActualType(varDsc->lvType) && !varTypeIsGC(targetType) && !varDsc->lvNormalizeOnLoad())
+            {
+                assert(!varTypeIsGC(varDsc));
+                targetType = genActualType(varDsc->lvType);
+            }
+            instruction ins  = ins_Load(targetType, compiler->isSIMDTypeLocalAligned(lcl->gtLclNum));
+            emitAttr    attr = emitTypeSize(targetType);
+            emitter*    emit = getEmitter();
 
             // Fixes Issue #3326
             attr = varTypeIsFloating(targetType) ? attr : emit->emitInsAdjustLoadStoreAttr(ins, attr);