ARM: dts: exynos: Move some assigned-clock* properties to i2s0 node

Setting of an IP block clock parent clock should be in the IP's DT node,
this ensures respective driver sees correct parent clock right from the
beginning, i.e. right after registering clock provider in probe() callback.

Without this change wrong I2S function clock (op_clk) is being used by
the driver in runtime suspend/resume ops, i.e. i2s_bus is enabled/disabled
twice instead of having activated both i2s_bus and sclk_i2s when required.

Change-Id: I1b52e20ff3596dae7b09d6a65d8ac6da7b76fe7d
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 0c2f1ef..f501f29 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -36,8 +36,7 @@
                compatible = "samsung,odroid-xu3-audio";
                model = "Odroid-XU4";
 
-               assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
-                               <&clock CLK_MOUT_EPLL>,
+               assigned-clocks = <&clock CLK_MOUT_EPLL>,
                                <&clock CLK_MOUT_MAU_EPLL>,
                                <&clock CLK_MOUT_USER_MAU_EPLL>,
                                <&clock_audss EXYNOS_MOUT_AUDSS>,
@@ -46,8 +45,7 @@
                                <&clock_audss EXYNOS_DOUT_AUD_BUS>,
                                <&clock_audss EXYNOS_DOUT_I2S>;
 
-               assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
-                               <&clock CLK_FOUT_EPLL>,
+               assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
                                <&clock CLK_MOUT_EPLL>,
                                <&clock CLK_MOUT_MAU_EPLL>,
                                <&clock CLK_MAU_EPLL>,
@@ -58,7 +56,6 @@
                                <0>,
                                <0>,
                                <0>,
-                               <0>,
                                <196608001>,
                                <(196608002 / 2)>,
                                <196608000>;
@@ -82,6 +79,8 @@
 
 &i2s0 {
        status = "okay";
+       assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+       assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
 };
 
 &pwm {