Merge tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm...

Daniel writes:
Highlights:
- Imre's for_each_sg_pages rework (now also with the stolen mem backed
  case fixed with a hack) plus the drm prime sg list coalescing patch from
  Rahul Sharma. I have some follow-up cleanups pending, already acked by
  Andrew Morton.
- Some prep-work for the crazy no-pch/display-less platform by Ben.
- Some vlv patches, by far not all (Jesse et al).
- Clean up the HDMI/SDVO #define confusion (Paulo)
- gen2-4 vblank fixes from Ville.
- Unclaimed register warning fixes for hsw (Paulo). More still to come ...
- Complete pageflips which have been stuck in a gpu hang, should prevent
  stuck gl compositors (Ville).
- pm patches for vt-switchless resume (Jesse). Note that the i915 enabling
  is not (yet) included, that took a bit longer to settle. PM patches are
  acked by Rafael Wysocki.
- Minor fixlets all over from various people.

* tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm-intel: (79 commits)
  drm/i915: Implement WaSwitchSolVfFArbitrationPriority
  drm/i915: Set the VIC in AVI infoframe for SDVO
  drm/i915: Kill a strange comment about DPMS functions
  drm/i915: Correct sandybrige overclocking
  drm/i915: Introduce GEN7_FEATURES for device info
  drm/i915: Move num_pipes to intel info
  drm/i915: fixup pd vs pt confusion in gen6 ppgtt code
  style nit: Align function parameter continuation properly.
  drm/i915: VLV doesn't have HDMI on port C
  drm/i915: DSPFW and BLC regs are in the display offset range
  drm/i915: set conservative clock gating values on VLV v2
  drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2
  drm/i915: add more VLV IDs
  drm/i915: use VLV DIP routines on VLV v2
  drm/i915: add media well to VLV force wake routines v2
  drm/i915: don't use plane pipe select on VLV
  drm: modify pages_to_sg prime helper to create optimized SG table
  drm/i915: use for_each_sg_page for setting up the gtt ptes
  drm/i915: create compact dma scatter lists for gem objects
  drm/i915: handle walking compact dma scatter lists
  ...

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.c
index e9b5789,6c4b13c..0614aff
--- 1/drivers/gpu/drm/i915/i915_drv.c
--- 2/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -121,15 -121,8 +121,13 @@@ MODULE_PARM_DESC(i915_enable_ppgtt
  unsigned int i915_preliminary_hw_support __read_mostly = 0;
  module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
  MODULE_PARM_DESC(preliminary_hw_support,
-               "Enable preliminary hardware support. "
-               "Enable Haswell and ValleyView Support. "
-               "(default: false)");
+               "Enable preliminary hardware support. (default: false)");
  
 +int i915_disable_power_well __read_mostly = 0;
 +module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 +MODULE_PARM_DESC(disable_power_well,
 +               "Disable the power well when possible (default: false)");
 +
  static struct drm_driver driver;
  extern int intel_agp_enabled;
  

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9a48e1a,9830839..117ce38
--- 1/drivers/gpu/drm/i915/i915_gem_execbuffer.c
--- 2/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@@ -732,11 -730,9 +730,11 @@@ validate_exec_list(struct drm_i915_gem_
                   int count)
  {
        int i;
 +      int relocs_total = 0;
 +      int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
  
        for (i = 0; i < count; i++) {
-               char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
+               char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
                int length; /* limited by fault_in_pages_readable() */
  
                if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index 8fc93f9,662a185..fe111f1
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -851,9 -798,9 +808,9 @@@ intel_dp_set_m_n(struct drm_crtc *crtc
         * set up for 8-bits of R/G/B, or 3 bytes total.
         */
        intel_link_compute_m_n(intel_crtc->bpp, lane_count,
 -                             mode->clock, adjusted_mode->clock, &m_n);
 +                             target_clock, adjusted_mode->clock, &m_n);
  
-       if (IS_HASWELL(dev)) {
+       if (HAS_DDI(dev)) {
                I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
                           TU_SIZE(m_n.tu) | m_n.gmch_m);
                I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);

diff --cc drivers/gpu/drm/i915/intel_panel.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
index adca007,ce3db2c..2de6da6
--- 1/drivers/gpu/drm/i915/intel_pm.c
--- 2/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -4076,12 -4092,9 +4092,12 @@@ void intel_set_power_well(struct drm_de
        bool is_enabled, enable_requested;
        uint32_t tmp;
  
-       if (!IS_HASWELL(dev))
+       if (!HAS_POWER_WELL(dev))
                return;
  
 +      if (!i915_disable_power_well && !enable)
 +              return;
 +
        tmp = I915_READ(HSW_PWR_WELL_DRIVER);
        is_enabled = tmp & HSW_PWR_WELL_STATE;
        enable_requested = tmp & HSW_PWR_WELL_ENABLE;