zero_bits_compound-1.c: Support aarch64.

2016-06-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>

gcc/testsuite/ChangeLog:
	* gcc.dg/zero_bits_compound-1.c: Support aarch64.
	* gcc.dg/zero_bits_compound-1.c: Likewise.

From-SVN: r237430

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dfe4fb7..248064d 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * gcc.dg/zero_bits_compound-1.c: Support aarch64.
+       * gcc.dg/zero_bits_compound-1.c: Likewise.
+
 2016-06-14  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/71522

diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
index d78dc43..650da60 100644 (file)
--- a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
+++ b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
@@ -4,7 +4,7 @@
 /* Note: This test requires that char, int and long have different sizes and the
    target has a way to do 32 -> 64 bit zero extension other than AND.  */
 
-/* { dg-do compile { target x86_64-*-* s390*-*-* } } */
+/* { dg-do compile { target x86_64-*-* s390*-*-* aarch64*-*-* } } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-options "-O3 -dP" } */
 

diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-2.c b/gcc/testsuite/gcc.dg/zero_bits_compound-2.c
index 80fd363..f282b94 100644 (file)
--- a/gcc/testsuite/gcc.dg/zero_bits_compound-2.c
+++ b/gcc/testsuite/gcc.dg/zero_bits_compound-2.c
@@ -1,7 +1,7 @@
 /* Test whether an AND mask or'ed with the know zero bits that equals a mode
    mask is a candidate for zero extendion.  */
 
-/* { dg-do compile { target x86_64-*-* s390*-*-* } } */
+/* { dg-do compile { target x86_64-*-* s390*-*-* aarch64*-*-* } } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-options "-O3 -dP" } */