/* We got an interrupt, didn't handle it. */
if (kick_irq) {
state->mphi_int_count++;
- FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+ FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
}
FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
/* Force a clear before another dummy send */
FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
- FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
+ FIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);
FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
}
dma_addr_t dma_base;
struct fiq_dma_blob *fiq_dmab;
void *dummy_send;
+ dma_addr_t dummy_send_dma;
gintmsk_data_t gintmsk_saved;
haintmsk_data_t haintmsk_saved;
int mphi_int_count;
DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
+ DWC_DMA_FREE(dev, 16, dwc_otg_hcd->fiq_state->dummy_send,
+ dwc_otg_hcd->fiq_state->dummy_send_dma);
DWC_FREE(dwc_otg_hcd->fiq_state);
#ifdef DWC_DEV_SRPCAP
for (i = 0; i < num_channels; i++) {
hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
}
- hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
+ hcd->fiq_state->dummy_send = DWC_DMA_ALLOC_ATOMIC(dev, 16,
+ &hcd->fiq_state->dummy_send_dma);
hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
if (!hcd->fiq_stack) {