Output more information in VME output buffer for Inter frame
authorXiang, Haihao <haihao.xiang@intel.com>
Thu, 5 Apr 2012 07:51:25 +0000 (15:51 +0800)
committerXiang, Haihao <haihao.xiang@intel.com>
Fri, 6 Apr 2012 08:07:02 +0000 (16:07 +0800)
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
src/shaders/vme/inter_frame.asm
src/shaders/vme/inter_frame.g6b
src/shaders/vme/inter_frame.g7b
src/shaders/vme/vme.inc

index 16fb1c6..aba5bc7 100644 (file)
@@ -82,6 +82,8 @@ send (8)
 /*
  * Oword Block Write message
  */
+
+/* MV pairs */        
 mov  (8) msg_reg0.0<1>:UD       obw_m0.0<8,8,1>:UD {align1};
 
 #ifdef DEV_SNB        
@@ -96,7 +98,29 @@ mov  (8) msg_reg1.0<1>:UD       obw_m1.0<8,8,0>:UD   {align1};
 
 mov  (8) msg_reg2.0<1>:UD       obw_m1.0<8,8,0>:UD   {align1};
 
-/* bind index 3, write 4 oword, msg type: 8(OWord Block Write) */
+/* bind index 3, write 8 oword, msg type: 8(OWord Block Write) */
+send (16)
+        msg_ind
+        obw_wb
+        null
+        data_port(
+                OBW_CACHE_TYPE,
+                OBW_MESSAGE_TYPE,
+                OBW_CONTROL_4,
+                OBW_BIND_IDX,
+                OBW_WRITE_COMMIT_CATEGORY,
+                OBW_HEADER_PRESENT
+        )
+        mlen 5
+        rlen obw_wb_length
+        {align1};
+
+/* other info */        
+add             (1)     msg_reg0.8<1>:UD        obw_m0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1} ;        
+mov             (1)     msg_reg1.0<1>:UD        vme_wb0.0<0,1,0>:UD     {align1};
+mov             (1)     msg_reg1.4<1>:UD        vme_wb0.28<0,1,0>:UD    {align1};
+        
+/* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
 send (16)
         msg_ind
         obw_wb
@@ -104,12 +128,12 @@ send (16)
         data_port(
                 OBW_CACHE_TYPE,
                 OBW_MESSAGE_TYPE,
-                OBW_CONTROL_3,
+                OBW_CONTROL_0,
                 OBW_BIND_IDX,
                 OBW_WRITE_COMMIT_CATEGORY,
                 OBW_HEADER_PRESENT
         )
-        mlen 3
+        mlen 2
         rlen obw_wb_length
         {align1};
 
index bf5844d..feec9fc 100644 (file)
    { 0x00000040, 0x24a23dad, 0x004504a2, 0xffd0ffd0 },
    { 0x00600001, 0x20200022, 0x008c04a0, 0x00000000 },
    { 0x00600001, 0x20400022, 0x008c04a0, 0x00000000 },
-   { 0x05800031, 0x22001cdd, 0x00000000, 0x061b0303 },
+   { 0x05800031, 0x22001cdd, 0x00000000, 0x0a1b0403 },
+   { 0x00000040, 0x20080c22, 0x00000488, 0x00000008 },
+   { 0x00000001, 0x20200022, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x20240022, 0x0000019c, 0x00000000 },
+   { 0x05800031, 0x22001cdd, 0x00000000, 0x041b0003 },
    { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 },
    { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 },
    { 0x00000040, 0x24403dad, 0x00000440, 0x00100010 },
@@ -39,6 +43,6 @@
    { 0x00010040, 0x24423dad, 0x00000442, 0x00100010 },
    { 0x00000040, 0x24882c21, 0x00000488, 0x000a000a },
    { 0x01000040, 0x20a63dad, 0x020000a6, 0xffffffff },
-   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffce },
+   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffc6 },
    { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
    { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 },
index 06408f4..6b60220 100644 (file)
    { 0x00200001, 0x24a002a9, 0x004501a0, 0x00000000 },
    { 0x00600001, 0x28200021, 0x008c04a0, 0x00000000 },
    { 0x00600001, 0x28400021, 0x008c04a0, 0x00000000 },
-   { 0x0a800031, 0x20001cac, 0x00000800, 0x060a0303 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 },
+   { 0x00000040, 0x28080c21, 0x00000488, 0x00000008 },
+   { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+   { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 },
+   { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 },
    { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 },
    { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 },
    { 0x01000010, 0x20004528, 0x000000a2, 0x000000a0 },
@@ -33,6 +37,6 @@
    { 0x00010040, 0x244a2d29, 0x0000044a, 0x00100010 },
    { 0x00000040, 0x24882c21, 0x00000488, 0x000a000a },
    { 0x01000040, 0x20a63dad, 0x020000a6, 0xffffffff },
-   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffd8 },
+   { 0x00110020, 0x34001c00, 0x02001400, 0xffffffd0 },
    { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
    { 0x07800031, 0x24001ca8, 0x00000800, 0x82000010 },
index 68fcada..b38c32a 100644 (file)
@@ -86,6 +86,7 @@ define(`OBW_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
 define(`OBW_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
 define(`OBW_CONTROL_2',                 `2')    /* 2 OWords */
 define(`OBW_CONTROL_3',                 `3')    /* 4 OWords */
+define(`OBW_CONTROL_4',                 `4')    /* 8 OWords */
 
 #ifdef DEV_SNB