drm/i915: Add WA for planes ending close to left screen edge

While running the kms_plane clipping test I noticed a similar problem to
the one described in Display WA #1175. In this case, similarly for
planes other than the cursor, with 1 or 3 pixels visible from the left
edge of the screen to the end of the plane and an odd plane X offset
used for clipping causes the same kind of underflow and display
corruption as described for WA #1175. Fix this in a similar way as that
WA rejecting planes ending <4 pixels from the left screen edge.

v2:
- Rebase on v2 of patch 1/1.

Testcase: igt/kms_plane/plane-clipping-pipe-*-planes
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180116112415.22060-2-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eba716e..f246ae2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2959,12 +2959,16 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
         * Planes other than the cursor may cause FIFO underflow and display
         * corruption if starting less than 4 pixels from the right edge of
         * the screen.
+        * Besides the above WA fix the similar problem, where planes other
+        * than the cursor ending less than 4 pixels from the left edge of the
+        * screen may cause FIFO underflow and display corruption.
         */
        if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
-           dst_x > pipe_src_w - 4) {
-               DRM_DEBUG_KMS("requested plane X start position %d invalid (valid range %d-%d)\n",
-                             dst_x,
-                             0, pipe_src_w - 4);
+           (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
+               DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
+                             dst_x + w < 4 ? "end" : "start",
+                             dst_x + w < 4 ? dst_x + w : dst_x,
+                             4, pipe_src_w - 4);
                return -ERANGE;
        }