gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmation

Ported from Vulkan.
Not sure what this is good for.. maybe write confirmation from L2 flushes?

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h
index 5775746..76c5c4f 100644 (file)
--- a/src/amd/common/r600d_common.h
+++ b/src/amd/common/r600d_common.h
@@ -67,6 +67,9 @@
 #define                COPY_DATA_WR_CONFIRM            (1 << 20)
 #define PKT3_EVENT_WRITE                       0x46
 #define PKT3_EVENT_WRITE_EOP                   0x47
+#define         EOP_INT_SEL(x)                          ((x) << 24)
+#define                        EOP_INT_SEL_NONE                        0
+#define                        EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM  3
 #define         EOP_DATA_SEL(x)                         ((x) << 29)
 #define                        EOP_DATA_SEL_DISCARD            0
 #define                        EOP_DATA_SEL_VALUE_32BIT        1

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 7226fc2..7c12565 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -109,6 +109,12 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
        unsigned op = EVENT_TYPE(event) |
                      EVENT_INDEX(5) |
                      event_flags;
+       unsigned sel = EOP_DATA_SEL(data_sel);
+
+       /* Wait for write confirmation before writing data, but don't send
+        * an interrupt. */
+       if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
+               sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
 
        if (ctx->chip_class >= GFX9) {
                /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
@@ -136,7 +142,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
 
                radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
                radeon_emit(cs, op);
-               radeon_emit(cs, EOP_DATA_SEL(data_sel));
+               radeon_emit(cs, sel);
                radeon_emit(cs, va);            /* address lo */
                radeon_emit(cs, va >> 32);      /* address hi */
                radeon_emit(cs, new_fence);     /* immediate data lo */
@@ -155,7 +161,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
                        radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
                        radeon_emit(cs, op);
                        radeon_emit(cs, va);
-                       radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
+                       radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
                        radeon_emit(cs, 0); /* immediate data */
                        radeon_emit(cs, 0); /* unused */
 
@@ -166,7 +172,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
                radeon_emit(cs, op);
                radeon_emit(cs, va);
-               radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
+               radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
                radeon_emit(cs, new_fence); /* immediate data */
                radeon_emit(cs, 0); /* unused */
        }