nir_emit_global_atomic should utilize lsc_op_num_data_values to
infer the number of operands for global atomic ops, following the same
pattern as nir_emit_surface_atomic
Fixes: 90a2137 ('intel/compiler: Use LSC opcode enum rather than legacy BRW_AOPs')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26432>
(cherry picked from commit
db6aaa691d05ef017b803d11cce4e341d1a98882)
"description": "intel/compiler: infer the number of operands using lsc_op_num_data_values",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": "90a2137cd56179a2c65339b2b60991e0281c8995",
"notes": null
nir_intrinsic_instr *instr)
{
int op = lsc_aop_for_nir_intrinsic(instr);
+ int num_data = lsc_op_num_data_values(op);
fs_reg dest = get_nir_def(instr->def);
fs_reg addr = get_nir_src(instr->src[0]);
fs_reg data;
- if (op != LSC_OP_ATOMIC_INC && op != LSC_OP_ATOMIC_DEC)
+ if (num_data >= 1)
data = expand_to_32bit(bld, get_nir_src(instr->src[1]));
- if (op == LSC_OP_ATOMIC_CMPXCHG) {
+ if (num_data >= 2) {
fs_reg tmp = bld.vgrf(data.type, 2);
fs_reg sources[2] = {
data,