Do not select tSXTB / tSXTH in thumb2 mode.

llvm-svn: 76600

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index fb0387213cc57ddedeb9741a2439b0a28f230b03..861b468c2d20917773c56b13722a26fca23ba633 100644 (file)
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -624,10 +624,10 @@ def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
 
 // If it's possible to use [r,r] address mode for sextload, select to
 // ldr{b|h} + sxt{b|h} instead.
-def : TPat<(sextloadi8 t_addrmode_s1:$addr),
-           (tSXTB (tLDRB t_addrmode_s1:$addr))>;
-def : TPat<(sextloadi16 t_addrmode_s2:$addr),
-           (tSXTH (tLDRH t_addrmode_s2:$addr))>;
+def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
+            (tSXTB (tLDRB t_addrmode_s1:$addr))>;
+def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
+            (tSXTH (tLDRH t_addrmode_s2:$addr))>;
 
 
 // Large immediate handling.

diff --git a/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
new file mode 100644 (file)
index 0000000..98979b5
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
@@ -0,0 +1,34 @@
+; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2
+; rdar://7076238
+
+@"\01LC" = external constant [36 x i8], align 1                ; <[36 x i8]*> [#uses=1]
+
+define arm_apcscc i32 @getUnknown(i32, ...) nounwind {
+entry:
+       %1 = load i8** undef, align 4           ; <i8*> [#uses=3]
+       %2 = getelementptr i8* %1, i32 4                ; <i8*> [#uses=1]
+       %3 = getelementptr i8* %1, i32 8                ; <i8*> [#uses=1]
+       %4 = bitcast i8* %2 to i32*             ; <i32*> [#uses=1]
+       %5 = load i32* %4, align 4              ; <i32> [#uses=1]
+       %6 = trunc i32 %5 to i8         ; <i8> [#uses=1]
+       %7 = getelementptr i8* %1, i32 12               ; <i8*> [#uses=1]
+       %8 = bitcast i8* %3 to i32*             ; <i32*> [#uses=1]
+       %9 = load i32* %8, align 4              ; <i32> [#uses=1]
+       %10 = trunc i32 %9 to i16               ; <i16> [#uses=1]
+       %11 = bitcast i8* %7 to i32*            ; <i32*> [#uses=1]
+       %12 = load i32* %11, align 4            ; <i32> [#uses=1]
+       %13 = trunc i32 %12 to i16              ; <i16> [#uses=1]
+       %14 = load i32* undef, align 4          ; <i32> [#uses=2]
+       %15 = sext i8 %6 to i32         ; <i32> [#uses=2]
+       %16 = sext i16 %10 to i32               ; <i32> [#uses=2]
+       %17 = sext i16 %13 to i32               ; <i32> [#uses=2]
+       %18 = call arm_apcscc  i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind              ; <i32> [#uses=0]
+       %19 = add i32 0, %15            ; <i32> [#uses=1]
+       %20 = add i32 %19, %16          ; <i32> [#uses=1]
+       %21 = add i32 %20, %14          ; <i32> [#uses=1]
+       %22 = add i32 %21, %17          ; <i32> [#uses=1]
+       %23 = add i32 %22, 0            ; <i32> [#uses=1]
+       ret i32 %23
+}
+
+declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind