case nir_intrinsic_load_line_width:
case nir_intrinsic_load_aa_line_width:
case nir_intrinsic_load_fb_layers_v3d:
+ case nir_intrinsic_load_tcs_num_patches_amd:
+ case nir_intrinsic_load_ring_tess_factors_amd:
+ case nir_intrinsic_load_ring_tess_offchip_amd:
+ case nir_intrinsic_load_ring_tess_factors_offset_amd:
+ case nir_intrinsic_load_ring_tess_offchip_offset_amd:
is_divergent = false;
break;
case nir_intrinsic_mbcnt_amd:
case nir_intrinsic_elect:
case nir_intrinsic_load_tlb_color_v3d:
+ case nir_intrinsic_load_tess_rel_patch_id_amd:
is_divergent = true;
break;
# src[] = { store value, descriptor, base address, scalar offset }
intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1], indices=[BASE, WRITE_MASK, IS_SWIZZLED, SLC_AMD, MEMORY_MODES])
+# Descriptor where TCS outputs are stored for TES
+system_value("ring_tess_offchip_amd", 4)
+system_value("ring_tess_offchip_offset_amd", 1)
+# Descriptor where TCS outputs are stored for the HW tessellator
+system_value("ring_tess_factors_amd", 4)
+system_value("ring_tess_factors_offset_amd", 1)
+
+# Number of patches processed by each TCS workgroup
+system_value("tcs_num_patches_amd", 1)
+# Relative tessellation patch ID within the current workgroup
+system_value("tess_rel_patch_id_amd", 1)
+
# V3D-specific instrinc for tile buffer color reads.
#
# The hardware requires that we read the samples and components of a pixel
res = MAX2(src0, src1);
break;
}
+ case nir_intrinsic_load_tess_rel_patch_id_amd:
+ case nir_intrinsic_load_tcs_num_patches_amd:
+ /* Very generous maximum: TCS/TES executed by largest possible workgroup */
+ res = config->max_work_group_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u);
+ break;
default:
break;
}