ARM: dts: Add missing CPU frequencies for Exynos5422/5800

Add missing 2.0GHz, 1.9GHz & 1.8GHz OPPs (for A15 cores) and 1.4GHz
OPP (for A7 cores).  Also update common Odroid-XU3 Lite/XU3/XU4
thermal cooling maps to account for new OPPs.

Since some new OPPs are not available on all Exynos5422/5800 boards
modify dts files for Odroid XU3 Lite (limited to 1.8 GHz / 1.3 GHz) &
Peach Pi (limited to 2.0 GHz / 1.3 GHz) accordingly.

This patch uses maximum voltages for new OPPs. This is a temporary
solution till proper Exynos ASV support is added.

Also while at it fix the number of cooling down steps for big cores
(should be 11 instead of 12 on Odroid XU3 Lite and 14 on XU3/XU4).

Change-Id: I6bff20d0a6c5a0b9a0eff9b028ca00ac3ef56049
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 96489f0aea6e22abb85a763758c9682fc025c419..c916fb06cf83e1aa5f1c88ef81239da1f5140486 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -112,7 +112,7 @@
                                /*
                                 * When reaching cpu0_alert3, reduce CPU
                                 * by 2 steps. On Exynos5422/5800 that would
-                                * be: 1600 MHz and 1100 MHz.
+                                * (usually) be: 1800 MHz and 1200 MHz.
                                 */
                                map3 {
                                        trip = <&cpu0_alert3>;
@@ -124,16 +124,16 @@
                                };
                                /*
                                 * When reaching cpu0_alert4, reduce CPU
-                                * further, down to 600 MHz (12 steps for big,
-                                * 7 steps for LITTLE).
+                                * further, down to 600 MHz (14 steps for big,
+                                * 8 steps for LITTLE).
                                 */
-                               map5 {
+                               cooling0_map5: map5 {
                                        trip = <&cpu0_alert4>;
-                                       cooling-device = <&cpu0 3 7>;
+                                       cooling-device = <&cpu0 3 8>;
                                };
-                               map6 {
+                               cooling0_map6: map6 {
                                        trip = <&cpu0_alert4>;
-                                       cooling-device = <&cpu4 3 12>;
+                                       cooling-device = <&cpu4 3 14>;
                                };
                        };
                };
@@ -194,13 +194,13 @@
                                        trip = <&cpu1_alert3>;
                                        cooling-device = <&cpu4 0 2>;
                                };
-                               map5 {
+                               cooling1_map5: map5 {
                                        trip = <&cpu1_alert4>;
-                                       cooling-device = <&cpu0 3 7>;
+                                       cooling-device = <&cpu0 3 8>;
                                };
-                               map6 {
+                               cooling1_map6: map6 {
                                        trip = <&cpu1_alert4>;
-                                       cooling-device = <&cpu4 3 12>;
+                                       cooling-device = <&cpu4 3 14>;
                                };
                        };
                };
@@ -261,13 +261,13 @@
                                        trip = <&cpu2_alert3>;
                                        cooling-device = <&cpu4 0 2>;
                                };
-                               map5 {
+                               cooling2_map5: map5 {
                                        trip = <&cpu2_alert4>;
-                                       cooling-device = <&cpu0 3 7>;
+                                       cooling-device = <&cpu0 3 8>;
                                };
-                               map6 {
+                               cooling2_map6: map6 {
                                        trip = <&cpu2_alert4>;
-                                       cooling-device = <&cpu4 3 12>;
+                                       cooling-device = <&cpu4 3 14>;
                                };
                        };
                };
@@ -328,13 +328,13 @@
                                        trip = <&cpu3_alert3>;
                                        cooling-device = <&cpu4 0 2>;
                                };
-                               map5 {
+                               cooling3_map5: map5 {
                                        trip = <&cpu3_alert4>;
-                                       cooling-device = <&cpu0 3 7>;
+                                       cooling-device = <&cpu0 3 8>;
                                };
-                               map6 {
+                               cooling3_map6: map6 {
                                        trip = <&cpu3_alert4>;
-                                       cooling-device = <&cpu4 3 12>;
+                                       cooling-device = <&cpu4 3 14>;
                                };
                        };
                };

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index b73cf3d8a95eb32b2773565b83051581d2a4f839..217b317d3d6bf1ad56006ae5aa21b78deebca248 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -21,6 +21,52 @@
        compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
 };
 
+/*
+ * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
+ * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
+ * Therefore we need to update OPPs tables and thermal maps accordingly.
+ */
+&cluster_a15_opp_table {
+       /delete-node/opp-2000000000;
+       /delete-node/opp-1900000000;
+};
+
+&cluster_a7_opp_table {
+       /delete-node/opp-1400000000;
+};
+
+&cooling0_map5 {
+       cooling-device = <&cpu0 3 7>;
+};
+
+&cooling0_map6 {
+       cooling-device = <&cpu4 3 11>;
+};
+
+&cooling1_map5 {
+       cooling-device = <&cpu0 3 7>;
+};
+
+&cooling1_map6 {
+       cooling-device = <&cpu4 3 11>;
+};
+
+&cooling2_map5 {
+       cooling-device = <&cpu0 3 7>;
+};
+
+&cooling2_map6 {
+       cooling-device = <&cpu4 3 11>;
+};
+
+&cooling3_map5 {
+       cooling-device = <&cpu0 3 7>;
+};
+
+&cooling3_map6 {
+       cooling-device = <&cpu4 3 11>;
+};
+
 &pwm {
        /*
         * PWM 0 -- fan

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 52c79d1eb7418cf8a9e8507ed3e6070d736fd1ff..50c515306f08d8caa1c311728af97c05a1bc2015 100644 (file)
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -145,6 +145,15 @@
        vdd-supply = <&ldo9_reg>;
 };
 
+/*
+ * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
+ * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards.  Thus we need to
+ * update A7 OPPs table accordingly.
+ */
+&cluster_a7_opp_table {
+       /delete-property/opp-1400000000;
+};
+
 &cpu0 {
        cpu-supply = <&buck2_reg>;
 };

diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 9ddb6bacac5ac8ea7b8feb1e21566f545f1cd67c..4e2bd670b8e5b13970b5624912c3d35656cf21a7 100644 (file)
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -24,6 +24,21 @@
 };
 
 &cluster_a15_opp_table {
+       opp-2000000000 {
+               opp-hz = /bits/ 64 <2000000000>;
+               opp-microvolt = <1312500>;
+               clock-latency-ns = <140000>;
+       };
+       opp-1900000000 {
+               opp-hz = /bits/ 64 <1900000000>;
+               opp-microvolt = <1262500>;
+               clock-latency-ns = <140000>;
+       };
+       opp-1800000000 {
+               opp-hz = /bits/ 64 <1800000000>;
+               opp-microvolt = <1237500>;
+               clock-latency-ns = <140000>;
+       };
        opp-1700000000 {
                opp-microvolt = <1250000>;
        };
@@ -85,6 +100,11 @@
 };
 
 &cluster_a7_opp_table {
+       opp-1400000000 {
+               opp-hz = /bits/ 64 <1400000000>;
+               opp-microvolt = <1275000>;
+               clock-latency-ns = <140000>;
+       };
        opp-1300000000 {
                opp-microvolt = <1250000>;
        };