"is equivalent to an `S_CBRANCH` with extra math", so the subvector loop handling
in ACO is done according to the `s_cbranch` doc.
+## RDNA early rasterization
+
+The ISA documentation says about `s_endpgm`:
+
+> The hardware implicitly executes S_WAITCNT 0 and S_WAITCNT_VSCNT 0
+> before executing this instruction.
+
+What the doc doesn't say is that in case of NGG (and legacy VS) when there
+are no param exports, the driver sets `NO_PC_EXPORT=1` for optimal performance,
+and when this is set, the hardware will start clipping and rasterization
+as soon as it encounters a position export with `DONE=1`, without waiting
+for the NGG (or VS) to finish.
+
+It can even launch PS waves before NGG (or VS) ends.
+
+When this happens, any store performed by a VS is not guaranteed
+to be complete when PS tries to load it, so we need to manually
+make sure to insert wait instructions before the position exports.
+
# Hardware Bugs
## SMEM corrupts VCCZ on SI/CI
pos_written |= 1 << 3;
outinfo->pos_exports = util_bitcount(pos_written);
+
+ /* GFX10+ early rasterization:
+ * When there are no param exports in an NGG (or legacy VS) shader,
+ * RADV sets NO_PC_EXPORT=1, which means the HW will start clipping and rasterization
+ * as soon as it encounters a DONE pos export. When this happens, PS waves can launch
+ * before the NGG (or VS) waves finish.
+ */
+ ctx->program->early_rast = ctx->program->chip_class >= GFX10 &&
+ outinfo->param_exports == 0;
}
void
bool xnack_enabled = false;
bool sram_ecc_enabled = false;
bool has_fast_fma32 = false;
+ bool early_rast = false; /* whether rasterization can start as soon as the 1st DONE pos export */
bool needs_vcc = false;
bool needs_flat_scr = false;