arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1

Add properties related to eMMC HS400 mode for esdhc1.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
index 60f5a4e..d1e4a85 100644 (file)
--- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
@@ -5,7 +5,7 @@
  * Some assumptions are made:
  *    * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  *
  */
 
@@ -56,3 +56,9 @@
                reg = <0x3>;
        };
 };
+
+&esdhc1 {
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       bus-width = <8>;
+};

diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
index 8e11b06..e9a743b 100644 (file)
--- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
@@ -6,7 +6,7 @@
  *    * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
  *    * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  *
  */
 
@@ -59,3 +59,9 @@
                reg = <0x1>;
        };
 };
+
+&esdhc1 {
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       bus-width = <8>;
+};

diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
index faf4285..d9ad1c6 100644 (file)
--- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
@@ -6,7 +6,7 @@
  *    * Mezzanine card M8 is connected to IO SLOT1
  *        (xlaui4 for DPMAC 1)
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  *
  */
 
@@ -24,3 +24,9 @@
                reg = <0x0>;
        };
 };
+
+&esdhc1 {
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       bus-width = <8>;
+};

diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index 341610c..0ca30df 100644 (file)
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -2,7 +2,7 @@
 /*
  * NXP LX2162AQDS device tree source
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  *
  */
 
@@ -135,3 +135,9 @@
                reg = <2>;
        };
 };
+
+&esdhc1 {
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       bus-width = <8>;
+};