ASoC: SOF: Intel: hda-stream: rename CL_SD_CTL registers as SD_CTL

The use of the CL prefix is misleading. HDaudio streams are used for
code loading since ApolloLake, but they are also used for regular
audio transfers.

No functionality change, pure rename.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20221024165310.246183-14-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sof/intel/hda-ctrl.c b/sound/soc/sof/intel/hda-ctrl.c
index 8a8b5f9..1290096 100644 (file)
--- a/sound/soc/sof/intel/hda-ctrl.c
+++ b/sound/soc/sof/intel/hda-ctrl.c
@@ -234,7 +234,7 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev)
        list_for_each_entry(stream, &bus->stream_list, list) {
                sd_offset = SOF_STREAM_SD_OFFSET(stream);
                snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                                 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+                                 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
                                  SOF_HDA_CL_DMA_SD_INT_MASK);
        }
 
@@ -300,7 +300,7 @@ void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
                sd_offset = SOF_STREAM_SD_OFFSET(stream);
                snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
                                        sd_offset +
-                                       SOF_HDA_ADSP_REG_CL_SD_CTL,
+                                       SOF_HDA_ADSP_REG_SD_CTL,
                                        SOF_HDA_CL_DMA_SD_INT_MASK,
                                        0);
        }
@@ -318,7 +318,7 @@ void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
        list_for_each_entry(stream, &bus->stream_list, list) {
                sd_offset = SOF_STREAM_SD_OFFSET(stream);
                snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                                 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+                                 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
                                  SOF_HDA_CL_DMA_SD_INT_MASK);
        }
 

diff --git a/sound/soc/sof/intel/hda-loader-skl.c b/sound/soc/sof/intel/hda-loader-skl.c
index 3211f56..69fdef8 100644 (file)
--- a/sound/soc/sof/intel/hda-loader-skl.c
+++ b/sound/soc/sof/intel/hda-loader-skl.c
@@ -141,7 +141,7 @@ static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable)
        u32 run = enable ? 0x1 : 0;
 
        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
                                HDA_CL_SD_CTL_RUN(1), HDA_CL_SD_CTL_RUN(run));
 
        retries = 300;
@@ -150,7 +150,7 @@ static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable)
 
                /* waiting for hardware to report the stream Run bit set */
                val = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
-                                      sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL);
+                                      sd_offset + SOF_HDA_ADSP_REG_SD_CTL);
                val &= HDA_CL_SD_CTL_RUN(1);
                if (enable && val)
                        break;
@@ -174,23 +174,23 @@ static void cl_skl_cldma_stream_clear(struct snd_sof_dev *sdev)
         * Descriptor Error Interrupt and set the cldma stream number to 0.
         */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
                                HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(0));
        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
                                HDA_CL_SD_CTL_STRM(0xf), HDA_CL_SD_CTL_STRM(0));
 
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, HDA_CL_SD_BDLPLBA(0));
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, HDA_CL_SD_BDLPLBA(0));
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0);
 
        /* Set the Cyclic Buffer Length to 0. */
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, 0);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 0);
        /* Set the Last Valid Index. */
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, 0);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 0);
 }
 
 static void cl_skl_cldma_setup_spb(struct snd_sof_dev *sdev,
@@ -240,27 +240,27 @@ static void cl_skl_cldma_setup_controller(struct snd_sof_dev *sdev,
 
        /* setting the stream register */
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
                          HDA_CL_SD_BDLPLBA(dmab_bdl->addr));
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
                          HDA_CL_SD_BDLPUBA(dmab_bdl->addr));
 
        /* Set the Cyclic Buffer Length. */
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, max_size);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_CBL, max_size);
        /* Set the Last Valid Index. */
        snd_sof_dsp_write(sdev, HDA_DSP_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, count - 1);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_LVI, count - 1);
 
        /* Set the Interrupt On Completion, FIFO Error Interrupt,
         * Descriptor Error Interrupt and the cldma stream number.
         */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
                                HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(1));
        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_CTL,
                                HDA_CL_SD_CTL_STRM(0xf),
                                HDA_CL_SD_CTL_STRM(1));
 }
@@ -439,7 +439,7 @@ static int cl_skl_cldma_wait_interruptible(struct snd_sof_dev *sdev,
 
        /* now check DMA interrupt status */
        cl_dma_intr_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
-                                             sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS);
+                                             sd_offset + SOF_HDA_ADSP_REG_SD_STS);
 
        if (!(cl_dma_intr_status & HDA_CL_DMA_SD_INT_COMPLETE)) {
                dev_err(sdev->dev, "cldma copy failed\n");

diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
index 3820454..3a4b0b6 100644 (file)
--- a/sound/soc/sof/intel/hda-loader.c
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -265,9 +265,9 @@ int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
 
        /* reset BDL address */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 0);
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0);
 
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
        snd_dma_free_pages(dmab);

diff --git a/sound/soc/sof/intel/hda-stream.c b/sound/soc/sof/intel/hda-stream.c
index 7ac7035..6d130b8 100644 (file)
--- a/sound/soc/sof/intel/hda-stream.c
+++ b/sound/soc/sof/intel/hda-stream.c
@@ -367,7 +367,7 @@ int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
 
                if (ret >= 0) {
                        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+                                         sd_offset + SOF_HDA_ADSP_REG_SD_STS,
                                          SOF_HDA_CL_DMA_SD_INT_MASK);
 
                        hstream->running = false;
@@ -419,10 +419,10 @@ int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_st
 
        /* reset BDL address */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
                          0x0);
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
                          0x0);
 
        hstream->frags = 0;
@@ -435,20 +435,20 @@ int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_st
 
        /* program BDL address */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
                          (u32)hstream->bdl.addr);
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
                          upper_32_bits(hstream->bdl.addr));
 
        /* program cyclic buffer length */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
                          hstream->bufsize);
 
        /* program last valid index */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
                                0xffff, (hstream->frags - 1));
 
        /* decouple host and link DMA, enable DSP features */
@@ -520,7 +520,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
        }
 
        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_STS,
                                SOF_HDA_CL_DMA_SD_INT_MASK,
                                SOF_HDA_CL_DMA_SD_INT_MASK);
 
@@ -534,10 +534,10 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 
        /* reset BDL address */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
                          0x0);
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
                          0x0);
 
        /* clear stream status */
@@ -562,7 +562,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
        }
 
        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_STS,
                                SOF_HDA_CL_DMA_SD_INT_MASK,
                                SOF_HDA_CL_DMA_SD_INT_MASK);
 
@@ -582,7 +582,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 
        /* program cyclic buffer length */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
                          hstream->bufsize);
 
        /*
@@ -606,7 +606,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
        /* program stream format */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
                                sd_offset +
-                               SOF_HDA_ADSP_REG_CL_SD_FORMAT,
+                               SOF_HDA_ADSP_REG_SD_FORMAT,
                                0xffff, hstream->format_val);
 
        if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
@@ -617,15 +617,15 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 
        /* program last valid index */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
-                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
+                               sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
                                0xffff, (hstream->frags - 1));
 
        /* program BDL address */
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
                          (u32)hstream->bdl.addr);
        snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
-                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
                          upper_32_bits(hstream->bdl.addr));
 
        /* enable position buffer, if needed */
@@ -649,7 +649,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
                hstream->fifo_size =
                        snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
                                         sd_offset +
-                                        SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE);
+                                        SOF_HDA_ADSP_REG_SD_FIFOSIZE);
                hstream->fifo_size &= 0xffff;
                hstream->fifo_size += 1;
        } else {

diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 6b1474d..b2a785d 100644 (file)
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -122,17 +122,17 @@
 #define SOF_HDA_ADSP_DPLBASE_ENABLE            0x01
 
 /* Stream Registers */
-#define SOF_HDA_ADSP_REG_CL_SD_CTL             0x00
-#define SOF_HDA_ADSP_REG_CL_SD_STS             0x03
-#define SOF_HDA_ADSP_REG_CL_SD_LPIB            0x04
-#define SOF_HDA_ADSP_REG_CL_SD_CBL             0x08
-#define SOF_HDA_ADSP_REG_CL_SD_LVI             0x0C
-#define SOF_HDA_ADSP_REG_CL_SD_FIFOW           0x0E
-#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE                0x10
-#define SOF_HDA_ADSP_REG_CL_SD_FORMAT          0x12
-#define SOF_HDA_ADSP_REG_CL_SD_FIFOL           0x14
-#define SOF_HDA_ADSP_REG_CL_SD_BDLPL           0x18
-#define SOF_HDA_ADSP_REG_CL_SD_BDLPU           0x1C
+#define SOF_HDA_ADSP_REG_SD_CTL                        0x00
+#define SOF_HDA_ADSP_REG_SD_STS                        0x03
+#define SOF_HDA_ADSP_REG_SD_LPIB               0x04
+#define SOF_HDA_ADSP_REG_SD_CBL                        0x08
+#define SOF_HDA_ADSP_REG_SD_LVI                        0x0C
+#define SOF_HDA_ADSP_REG_SD_FIFOW              0x0E
+#define SOF_HDA_ADSP_REG_SD_FIFOSIZE           0x10
+#define SOF_HDA_ADSP_REG_SD_FORMAT             0x12
+#define SOF_HDA_ADSP_REG_SD_FIFOL              0x14
+#define SOF_HDA_ADSP_REG_SD_BDLPL              0x18
+#define SOF_HDA_ADSP_REG_SD_BDLPU              0x1C
 #define SOF_HDA_ADSP_SD_ENTRY_SIZE             0x20
 
 /* CL: Software Position Based FIFO Capability Registers */