v4l2: mipi channel add reset control suppurt

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 8ed4aa9..d6632f9 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -595,19 +595,24 @@
                        reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
                                "isp0", "isp1", "trst", "pmu", "syscrg";
                        clocks = <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
-                                       <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
+                               <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
                        clock-names = "clk_ispcore_2x", "clk_isp_axi";
                        resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
-                                       <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
-                                       <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
-                                       <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
-                                       <&rstgen RSTN_U0_VIN_N_PCLK>,
-                                       <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
-                                       <&rstgen RSTN_U0_VIN_P_AXIRD>,
-                                       <&rstgen RSTN_U0_VIN_P_AXIWR>;
+                               <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
+                               <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
+                               <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
+                               <&rstgen RSTN_U0_VIN_N_PCLK>,
+                               <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
+                               <&rstgen RSTN_U0_VIN_P_AXIRD>,
+                               <&rstgen RSTN_U0_VIN_P_AXIWR>,
+                               <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
+                               <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
+                               <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
+                               <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>;
                        reset-names = "rst_isp_top_n", "rst_isp_top_axi", "rst_wrapper_p",
-                                               "rst_wrapper_c", "rst_pclk", "rst_sys_clk",
-                                               "rst_axird", "rst_axiwr";
+                               "rst_wrapper_c", "rst_pclk", "rst_sys_clk", "rst_axird",
+                               "rst_axiwr", "rst_pixel_clk_if0", "rst_pixel_clk_if1",
+                               "rst_pixel_clk_if2", "rst_pixel_clk_if3";
                        interrupts = <92 87 86>;
                        status = "disabled";
                };

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
index 56f2d8c..ee8f5fa 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
@@ -69,30 +69,32 @@ exit:
 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
 {
        struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
+       struct stfcamss *stfcamss = csi_dev->stfcamss;
 
-#if 0
-       // reg_set_highest_bit(vin->clkgen_base, CLK_CSI2RX0_APB_CTRL);
-       apb_clk_set(vin, 1);
-
-       if (csi_dev->id == 0) {
-               reg_set_bit(vin->clkgen_base,
-                               CLK_MIPI_RX0_PXL_CTRL,
-                               0x1F, 0x3);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_0_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_1_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_2_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_3_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_SYS0_CTRL);
-       } else {
-               reg_set_bit(vin->clkgen_base,
-                               CLK_MIPI_RX1_PXL_CTRL,
-                               0x1F, 0x3);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_0_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_1_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_2_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_3_CTRL);
-               reg_set_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_SYS1_CTRL);
-       }
+    reg_set_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0x3<<0);
+    reg_set_bit(vin->clkgen_base, CLK_U0_ISPV2_TOP_WRAPPER_CLK_C, BIT(24), 0x0<<24);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF0, BIT(31), 0x1<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF1, BIT(31), 0x1<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF2, BIT(31), 0x1<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF3, BIT(31), 0x1<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_CLK_P_AXIWR, BIT(24), 0x0<<24);
+
+#ifdef CONFIG_RESET_STARFIVE_JH7110
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rst);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rst);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rst);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rst);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rst);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rst);
+#else
+    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
+               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
+        BIT(4)|BIT(9));
+    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
+               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
+        BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(10));
+    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
+               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE, BIT(11));
 #endif
 
        return 0;
@@ -101,26 +103,28 @@ static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
 {
        struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
+       struct stfcamss *stfcamss = csi_dev->stfcamss;
 
-#if 0
-       // reg_clr_highest_bit(vin->clkgen_base, CLK_CSI2RX0_APB_CTRL);
-       apb_clk_set(vin, 0);
-
-       if (csi_dev->id == 0) {
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_0_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_1_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_2_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL_3_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX0_SYS0_CTRL);
-       } else {
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_0_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_1_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_2_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_PXL_3_CTRL);
-               reg_clr_highest_bit(vin->clkgen_base, CLK_MIPI_RX1_SYS1_CTRL);
-       }
+#ifdef CONFIG_RESET_STARFIVE_JH7110
+       reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rst);
+       reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rst);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rst);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rst);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rst);      
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rst);
+#else
+    reg_assert_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
+               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
+        BIT(6)|BIT(7)|BIT(8));
 #endif
 
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, BIT(31), 0x0<<31);
+
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF0, BIT(31), 0x0<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF1, BIT(31), 0x0<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF2, BIT(31), 0x0<<31);
+    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF3, BIT(31), 0x0<<31);
+
        return 0;
 }
 

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
index 382f899..df3a2ca 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
@@ -141,28 +141,6 @@ static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
 
        reg_set_bit(vin->clkgen_base,   CLK_U0_VIN_CLK_P_AXIWR, CLK_U0_VIN_MUX_SEL, 0x1<<24);
 
-#if 0
-    //disable first, need to check mipi config on EVB
-    reg_set_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0x3<<0);
-    reg_set_bit(vin->clkgen_base, CLK_U0_ISPV2_TOP_WRAPPER_CLK_C, BIT(24), 0x0<<24);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF0, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF1, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF2, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF3, BIT(31), 0x1<<31);
-
-
-    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-        BIT(4)|BIT(9));
-
-    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-        BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(10));
-
-    reg_set_bit(vin->clkgen_base,      CLK_U0_VIN_CLK_P_AXIWR, BIT(24), 0x0<<24);
-    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE, BIT(11));
-#endif
        return 0;
 }
 
@@ -187,20 +165,6 @@ static int stf_vin_clk_disable(struct stf_vin2_dev *vin_dev)
 
        reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, CLK_U0_VIN_PCLK_ICG, 0x0);
 
-#if 0
-    //disable first, need to check mipi config on EVB
-    reg_assert_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-        BIT(6)|BIT(7)|BIT(8));
-
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, BIT(31), 0x0<<31);
-
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF0, BIT(31), 0x0<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF1, BIT(31), 0x0<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF2, BIT(31), 0x0<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF3, BIT(31), 0x0<<31);
-#endif
-
        return 0;
 }
 
@@ -290,11 +254,11 @@ static void stf_vin_power_on(struct stf_vin2_dev *vin_dev,        int enable)
        } else {
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-                       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rst);
-                       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rst);
+               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rst);
+               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rst);
 #else
-                       reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(9));
-                       reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(10));
+               reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(9));
+               reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(10));
 #endif
 
 #ifdef CONFIG_CLK_STARFIVE_JH7110

diff --git a/drivers/media/platform/starfive/v4l2_driver/stfcamss.c b/drivers/media/platform/starfive/v4l2_driver/stfcamss.c
index 0d99644..9b5b91a 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stfcamss.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stfcamss.c
@@ -69,6 +69,10 @@ char *resets[] = {
        "rst_sys_clk",
        "rst_axird",
        "rst_axiwr",
+       "rst_pixel_clk_if0",
+       "rst_pixel_clk_if1",
+       "rst_pixel_clk_if2",
+       "rst_pixel_clk_if3",
 };
 
 int stfcamss_get_mem_res(struct platform_device *pdev, struct stf_vin_dev *vin)

diff --git a/drivers/media/platform/starfive/v4l2_driver/stfcamss.h b/drivers/media/platform/starfive/v4l2_driver/stfcamss.h
index 3921052..f7aed67 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stfcamss.h
+++ b/drivers/media/platform/starfive/v4l2_driver/stfcamss.h
@@ -56,6 +56,10 @@ enum stf_rst_num {
        STFRST_SYS_CLK,
        STFRST_AXIRD,
        STFRST_AXIWR,
+       STFRST_PIXEL_CLK_IF0,
+       STFRST_PIXEL_CLK_IF1,
+       STFRST_PIXEL_CLK_IF2,
+       STFRST_PIXEL_CLK_IF3,
        STFRST_NUM
 };