* config.gcc: Add m32c-elf support.
* doc/contrib.texi: Mention m32c.
* doc/extend.texi: Document m32c extensions.
* doc/install.texi: Mention m32c.
* doc/invoke.texi: Document m32c options.
* doc/md.texi: Document m32c constraints.
* config/m32c/addsub.md: New file.
* config/m32c/bitops.md: New file.
* config/m32c/cond.md: New file.
* config/m32c/jump.md: New file.
* config/m32c/m32c-lib1.S: New file.
* config/m32c/m32c-lib2.c: New file.
* config/m32c/m32c-modes.def: New file.
* config/m32c/m32c-pragma.c: New file.
* config/m32c/m32c-protos.h: New file.
* config/m32c/m32c.abi: New file.
* config/m32c/m32c.c: New file.
* config/m32c/m32c.h: New file.
* config/m32c/m32c.md: New file.
* config/m32c/m32c.opt: New file.
* config/m32c/minmax.md: New file.
* config/m32c/mov.md: New file.
* config/m32c/muldiv.md: New file.
* config/m32c/predicates.md: New file.
* config/m32c/prologue.md: New file.
* config/m32c/shift.md: New file.
* config/m32c/t-m32c: New file.
From-SVN: r102207
+2005-07-20 DJ Delorie <dj@redhat.com>
+
+ * config.gcc: Add m32c-elf support.
+
+ * doc/contrib.texi: Mention m32c.
+ * doc/extend.texi: Document m32c extensions.
+ * doc/install.texi: Mention m32c.
+ * doc/invoke.texi: Document m32c options.
+ * doc/md.texi: Document m32c constraints.
+
+ * config/m32c/addsub.md: New file.
+ * config/m32c/bitops.md: New file.
+ * config/m32c/cond.md: New file.
+ * config/m32c/jump.md: New file.
+ * config/m32c/m32c-lib1.S: New file.
+ * config/m32c/m32c-lib2.c: New file.
+ * config/m32c/m32c-modes.def: New file.
+ * config/m32c/m32c-pragma.c: New file.
+ * config/m32c/m32c-protos.h: New file.
+ * config/m32c/m32c.abi: New file.
+ * config/m32c/m32c.c: New file.
+ * config/m32c/m32c.h: New file.
+ * config/m32c/m32c.md: New file.
+ * config/m32c/m32c.opt: New file.
+ * config/m32c/minmax.md: New file.
+ * config/m32c/mov.md: New file.
+ * config/m32c/muldiv.md: New file.
+ * config/m32c/predicates.md: New file.
+ * config/m32c/prologue.md: New file.
+ * config/m32c/shift.md: New file.
+ * config/m32c/t-m32c: New file.
+
2005-07-20 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.md (UNSPEC_SP_SET, UNSPEC_SP_TEST): New constants.
cpu_type=`echo ${target} | sed 's/-.*$//'`
cpu_is_64bit=
case ${target} in
+m32c*-*-*)
+ cpu_type=m32c
+ tmake_file=m32c/t-m32c
+ ;;
alpha*-*-*)
cpu_type=alpha
need_64bit_hwint=yes
extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o"
use_collect2=no
;;
+m32c-*-elf*)
+ tm_file="dbxelf.h elfos.h svr4.h ${tm_file}"
+ c_target_objs="m32c-pragma.o"
+ cxx_target_objs="m32c-pragma.o"
+ use_fixproto=yes
+ ;;
*)
echo "*** Configuration ${target} not supported" 1>&2
exit 1
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; add, sub
+
+(define_insn "addqi3"
+ [(set (match_operand:QI 0 "mra_or_sp_operand"
+ "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm")
+ (plus:QI (match_operand:QI 1 "mra_operand"
+ "%0,0,0,0, 0,0,0,0")
+ (match_operand:QI 2 "mrai_operand"
+ "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa")))]
+ ""
+ "add.b\t%2,%0"
+ [(set_attr "flags" "oszc")]
+ )
+
+(define_insn "addhi3"
+ [(set (match_operand:HI 0 "nonimmediate_operand"
+ "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, !Rsp")
+ (plus:HI (match_operand:HI 1 "general_operand"
+ "%0,0,0,0, 0,0, Raw, 0")
+ (match_operand:HI 2 "general_operand"
+ "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, i")))]
+ ""
+ "@
+ add.w\t%2,%0
+ add.w\t%2,%0
+ add.w\t%2,%0
+ add.w\t%2,%0
+ sub.w\t%m2,%0
+ sub.w\t%m2,%0
+ mova\t%d2[%1],%0
+ add.w\t%2,%0"
+ [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc")]
+ )
+
+(define_insn "addpsi3"
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "=SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi,Rhi,&Rhi")
+ (plus:PSI (match_operand:PSI 1 "nonimmediate_operand" "0,0,0, Raa,Rad,!Rcl,Rhi")
+ (match_operand:PSI 2 "general_operand" "iSdRpi,?Rmm,i, i,IS2,i,!Rcl")))]
+ "TARGET_A24"
+ "@
+ add.%&\t%2,%0
+ add.%&\t%2,%0
+ add.%&\t%2,%0
+ mova\t%d2[%1],%0
+ mova\t%D2[%1],%0
+ #
+ #"
+ [(set_attr "flags" "oszc,oszc,oszc,*,*,oszc,oszc")]
+ )
+
+; This is needed for reloading large frames.
+(define_split
+ [(set (match_operand:PSI 0 "ra_operand" "")
+ (plus:PSI (match_operand:PSI 1 "cr_operand" "")
+ (match_operand:PSI 2 "immediate_operand" "")))]
+ ""
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0)
+ (plus:PSI (match_dup 0)
+ (match_dup 2)))]
+ ""
+ )
+
+; This is needed for reloading large frames.
+(define_split
+ [(set (match_operand:PSI 0 "ra_operand" "")
+ (plus:PSI (match_operand:PSI 1 "ra_operand" "")
+ (match_operand:PSI 2 "cr_operand" "")))]
+ ""
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0)
+ (plus:PSI (match_dup 0)
+ (match_dup 1)))]
+ ""
+ )
+
+(define_insn "subqi3"
+ [(set (match_operand:QI 0 "mra_or_sp_operand"
+ "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
+ (minus:QI (match_operand:QI 1 "mra_operand"
+ "0,0,0,0, 0,0,0,0, 0")
+ (match_operand:QI 2 "mrai_operand"
+ "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
+ ""
+ "sub.b\t%2,%0"
+ [(set_attr "flags" "oszc")]
+ )
+
+(define_insn "subhi3"
+ [(set (match_operand:HI 0 "mra_operand"
+ "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
+ (minus:HI (match_operand:HI 1 "mras_operand"
+ "0,0,0,0, 0,0")
+ (match_operand:HI 2 "mrai_operand"
+ "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
+ ""
+ "@
+ sub.w\t%2,%0
+ sub.w\t%2,%0
+ sub.w\t%2,%0
+ sub.w\t%2,%0
+ add.w\t%m2,%0
+ add.w\t%m2,%0"
+ [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
+ )
+
+(define_insn "subpsi3"
+ [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
+ (minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
+ (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
+ "TARGET_A24"
+ "sub.%&\t%2,%0"
+ [(set_attr "flags" "oszc")]
+ )
+
+(define_insn "negqi2"
+ [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
+ (neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
+ ""
+ "neg.b\t%0"
+ [(set_attr "flags" "oszc,oszc")]
+ )
+
+(define_insn "neghi2"
+ [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
+ (neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
+ ""
+ "neg.w\t%0"
+ [(set_attr "flags" "oszc,oszc")]
+ )
+
+; We can negate an SImode by operating on the subparts. GCC deals
+; with this itself for larger modes, but not SI.
+(define_insn "negsi2"
+ [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
+ (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
+ ""
+ "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
+ [(set_attr "flags" "oszc,oszc")]
+ )
+
+(define_insn "absqi2"
+ [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
+ (abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
+ ""
+ "abs.b\t%0"
+ [(set_attr "flags" "oszc")]
+ )
+
+(define_insn "abshi2"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+ (abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
+ ""
+ "abs.w\t%0"
+ [(set_attr "flags" "oszc")]
+ )
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; Bit-wise operations (and, ior, xor, shift)
+
+(define_insn "andqi3"
+ [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
+ (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+ ""
+ "and.b\t%x2,%0"
+ [(set_attr "flags" "sz,sz,sz,sz")]
+ )
+
+(define_insn "andhi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm,RhiSd,??Rmm")
+ (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,?Rmm,iRhiSd")))]
+ ""
+ "and.w\t%X2,%0"
+ [(set_attr "flags" "sz,sz,sz,sz")]
+ )
+
+(define_insn "iorqi3"
+ [(set (match_operand:QI 0 "mra_operand" "=RqiSd,??Rmm,RqiSd,??Rmm")
+ (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:QI 2 "mrai_operand" "iRhlSd,iRhlSd,?Rmm,?Rmm")))]
+ ""
+ "or.b\t%x2,%0"
+ [(set_attr "flags" "sz,sz,sz,sz")]
+ )
+
+(define_insn "iorhi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+ (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+ ""
+ "or.w\t%X2,%0"
+ [(set_attr "flags" "sz,sz,sz,sz")]
+ )
+
+(define_insn "xorqi3"
+ [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
+ (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+ ""
+ "xor.b\t%x2,%0"
+ [(set_attr "flags" "sz,sz,sz,sz")]
+ )
+
+(define_insn "xorhi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+ (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+ ""
+ "xor.w\t%X2,%0"
+ [(set_attr "flags" "sz,sz,sz,sz")]
+ )
+
+(define_insn "one_cmplqi2"
+ [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
+ (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
+ ""
+ "not.b\t%0"
+ [(set_attr "flags" "sz,sz")]
+ )
+
+(define_insn "one_cmplhi2"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+ (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
+ ""
+ "not.w\t%0"
+ [(set_attr "flags" "sz,sz")]
+ )
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+; conditionals - cmp, jcc, setcc, etc.
+
+; Until support for relaxing is supported in gas, we must assume that
+; short labels won't reach, so we must use long labels.
+; Unfortunately, there aren't any conditional jumps with long labels,
+; so instead we invert the conditional and jump around a regular jump.
+
+; Note that we can, at some point in the future, add code to omit the
+; "cmp" portion of the insn if the preceeding insn happened to set the
+; right flags already. For example, a mov followed by a "cmp *,0" is
+; redundant; the move already set the Z flag.
+
+(define_insn "cbranchqi4"
+ [(set (pc) (if_then_else
+ (match_operator 0 "m32c_cmp_operator"
+ [(match_operand:QI 1 "mrai_operand" "RqiSd,RqiSd,?Rmm,?Rmm")
+ (match_operand:QI 2 "mrai_operand" "iRqiSd,?Rmm,iRqiSd,?Rmm")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "cmp.b\t%2,%1\n\tj%C0\t1f\n\tjmp.a\t%l3\n1:"
+; "cmp.b\t%2,%1\n\tj%c0\t%l3"
+ [(set_attr "flags" "oszc,oszc,oszc,oszc")]
+ )
+
+(define_insn "cbranchhi4"
+ [(set (pc) (if_then_else
+ (match_operator 0 "m32c_cmp_operator"
+ [(match_operand:HI 1 "mrai_operand" "Rhi,?Sd,Rhi,?Sd,?Rmm,?Rmm")
+ (match_operand:HI 2 "mrai_operand" "iRhiSd,iRhiSd,?Rmm,?Rmm,iRhiSd,?Rmm")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "cmp.w\t%2,%1\n\tj%C0\t1f\n\tjmp.a\t%l3\n1:"
+; "cmp.w\t%2,%1\n\tj%c0\t%l3"
+ [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
+ )
+
+(define_insn "cbranchpsi4"
+ [(set (pc) (if_then_else
+ (match_operator 0 "m32c_cmp_operator"
+ [(match_operand:PSI 1 "mrai_operand" "RsiSd,RsiSd,?Rmm,?Rmm")
+ (match_operand:PSI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_A24"
+ "cmp.l\t%2,%1\n\tj%C0\t1f\n\tjmp.a\t%l3\n1:"
+; "cmp.l\t%2,%1\n\tj%c0\t%l3"
+ [(set_attr "flags" "oszc,oszc,oszc,oszc")]
+ )
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; jump, conditionals, calls, etc
+
+(define_insn "indirect_jump_16"
+ [(set (pc)
+ (match_operand:HI 0 "register_operand" "Rhi"))]
+ "TARGET_A16"
+; "jmpi.a\t%0"
+ ; no 16 bit jmpi in r8c
+ "push.b #0 | push.w\t%0 | rts"
+ )
+
+(define_insn "indirect_jump_24"
+ [(set (pc)
+ (match_operand:PSI 0 "register_operand" "Rpi"))]
+ "TARGET_A24"
+ "jmpi.a\t%0"
+ )
+
+(define_expand "indirect_jump"
+ [(match_operand 0 "register_operand" "")]
+ ""
+ "if (TARGET_A16)
+ emit_jump_insn (gen_indirect_jump_16(operands[0]));
+ else
+ emit_jump_insn (gen_indirect_jump_24(operands[0]));
+ DONE;"
+ )
+
+; We can replace this with jmp.s when gas supports relaxing. m32c
+; opcodes are too complicated to try to compute their sizes here, it's
+; far easier (and more reliable) to let gas worry about it.
+(define_insn "jump"
+ [(set (pc)
+ (label_ref (match_operand 0 "" "")))]
+ ""
+ "jmp.a\t%l0"
+)
+
+; No 16 bit indirect calls on r8c/m16c. */
+(define_insn "call"
+ [(call (match_operand:QI 0 "memory_operand" "Si,SaSb,?Rmm")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "immediate_operand" ""))]
+ ""
+ "*
+switch (which_alternative) {
+ case 0: return \"jsr.a\t%0\";
+ case 1: return TARGET_A16 ? \"push.w %a0 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a0\";
+ case 2: return \"jsri.a\t%a0\";
+}"
+ )
+
+(define_insn "call_value"
+ [(set (match_operand 0 "m32c_return_operand" "=RdiRmmRpa,RdiRmmRpa,RdiRmmRpa")
+ (call (match_operand:QI 1 "memory_operand" "Si,SaSb,?Rmm")
+ (match_operand 2 "" "")))
+ (use (match_operand 3 "immediate_operand" ""))]
+ ""
+ "*
+switch (which_alternative) {
+ case 0: return \"jsr.a\t%1\";
+ case 1: return TARGET_A16 ? \"push.w %a1 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a1\";
+ case 2: return \"jsri.a\t%a1\";
+}"
+ )
--- /dev/null
+/* libgcc routines for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ In addition to the permissions in the GNU General Public License,
+ the Free Software Foundation gives you unlimited permission to link
+ the compiled version of this file into combinations with other
+ programs, and to distribute those combinations without any
+ restriction coming from the use of this file. (The General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into a combine executable.)
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
+#define A16
+#define A(n,w) n
+#define W w
+#else
+#define A24
+#define A(n,w) w
+#define W l
+#endif
+
+
+#ifdef L__m32c_memregs
+
+/* Warning: these memory locations are used as a register bank. They
+ *must* end up consecutive in any final executable, so you may *not*
+ use the otherwise obvious ".comm" directive to allocate space for
+ them. */
+
+ .bss
+ .global mem0
+mem0: .space 1
+ .global mem1
+mem1: .space 1
+ .global mem2
+mem2: .space 1
+ .global mem3
+mem3: .space 1
+ .global mem4
+mem4: .space 1
+ .global mem5
+mem5: .space 1
+ .global mem6
+mem6: .space 1
+ .global mem7
+mem7: .space 1
+ .global mem8
+mem8: .space 1
+ .global mem9
+mem9: .space 1
+ .global mem10
+mem10: .space 1
+ .global mem11
+mem11: .space 1
+ .global mem12
+mem12: .space 1
+ .global mem13
+mem13: .space 1
+ .global mem14
+mem14: .space 1
+ .global mem15
+mem15: .space 1
+
+#endif
+
+#ifdef L__m32c_eh_return
+ .text
+ .global __m32c_eh_return
+__m32c_eh_return:
+
+ /* At this point, r0 has the stack adjustment, r1r3 has the
+ address to return to. The stack looks like this:
+
+ old_ra
+ old_fp
+ <- unwound sp
+ ...
+ fb
+ through
+ r0
+ <- sp
+
+ What we need to do is restore all the registers, update the
+ stack, and return to the right place.
+ */
+
+ stc sp,a0
+
+ add.W A(#16,#24),a0
+ /* a0 points to the current stack, just above the register
+ save areas */
+
+ mov.w a0,a1
+ exts.w r0
+ sub.W A(r0,r0r2),a1
+ sub.W A(#3,#4),a1
+ /* a1 points to the new stack. */
+
+ /* This is for the "rts" below. */
+ mov.w r1,[a1]
+#ifdef A16
+ mov.w r2,r1
+ mov.b r1l,2[a1]
+#else
+ mov.w r2,2[a1]
+#endif
+
+ /* This is for the "popc sp" below. */
+ mov.W a1,[a0]
+
+ popm r0,r1,r2,r3,a0,a1,sb,fb
+ popc sp
+ rts
+#endif
+
+/* SImode arguments for SI foo(SI,SI) functions. */
+#ifdef A16
+#define SAL 5[fb]
+#define SAH 7[fb]
+#define SBL 9[fb]
+#define SBH 11[fb]
+#else
+#define SAL 8[fb]
+#define SAH 10[fb]
+#define SBL 12[fb]
+#define SBH 14[fb]
+#endif
+
+#ifdef L__m32c_mulsi3
+ .text
+ .global ___mulsi3
+___mulsi3:
+ enter #0
+ push.w r2
+ mov.w SAL,mem0
+ mov.w SAH,mem2
+ mulu.w SBL,mem0 /* writes to r2r0 */
+ mov.w SAL,r0
+ mulu.w SBH,r0 /* writes to r2r0 */
+ add.w r0,mem2
+ mov.w SAH,r0
+ mulu.w SBL,r0
+ add.w r0,mem2
+ pop.w r2
+ exitd
+#endif
+
+#ifdef L__m32c_cmpsi2
+ .text
+ .global ___cmpsi2
+___cmpsi2:
+ enter #0
+ cmp.w SBH,SAH
+ jgt cmpsi_gt
+ jlt cmpsi_lt
+ cmp.w SBL,SAL
+ jgt cmpsi_gt
+ jlt cmpsi_lt
+ mov.w #1,r0
+ exitd
+cmpsi_gt:
+ mov.w #2,r0
+ exitd
+cmpsi_lt:
+ mov.w #0,r0
+ exitd
+#endif
+
+#ifdef L__m32c_ucmpsi2
+ .text
+ .global ___ucmpsi2
+___ucmpsi2:
+ enter #0
+ cmp.w SBH,SAH
+ jgtu cmpsi_gt
+ jltu cmpsi_lt
+ cmp.w SBL,SAL
+ jgtu cmpsi_gt
+ jltu cmpsi_lt
+ mov.w #1,r0
+ exitd
+cmpsi_gt:
+ mov.w #2,r0
+ exitd
+cmpsi_lt:
+ mov.w #0,r0
+ exitd
+#endif
+
+#ifdef L__m32c_jsri16
+ .data
+m32c_jsri_addr:
+ .byte 0, 0, 0
+m32c_jsri_ret:
+ .byte 0, 0, 0
+
+ .text
+ .global m32c_jsri16
+m32c_jsri16:
+ pop.w m32c_jsri_ret
+ pop.b m32c_jsri_ret+2
+ pop.w m32c_jsri_addr
+ push.b m32c_jsri_ret+2
+ push.w m32c_jsri_ret
+ jmpi.a m32c_jsri_addr
+
+#endif
--- /dev/null
+/* libgcc routines for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ In addition to the permissions in the GNU General Public License,
+ the Free Software Foundation gives you unlimited permission to link
+ the compiled version of this file into combinations with other
+ programs, and to distribute those combinations without any
+ restriction coming from the use of this file. (The General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into a combine executable.)
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+typedef int HItype __attribute__ ((mode (HI)));
+typedef unsigned int UHItype __attribute__ ((mode (HI)));
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+USItype udivmodsi4 (USItype num, USItype den, word_type modwanted);
+SItype __divsi3 (SItype a, SItype b);
+SItype __modsi3 (SItype a, SItype b);
+SItype __udivsi3 (SItype a, SItype b);
+SItype __umodsi3 (SItype a, SItype b);
+
+USItype
+udivmodsi4 (USItype num, USItype den, word_type modwanted)
+{
+ USItype bit = 1;
+ USItype res = 0;
+
+ while (den < num && bit && !(den & (1L << 31)))
+ {
+ den <<= 1;
+ bit <<= 1;
+ }
+ while (bit)
+ {
+ if (num >= den)
+ {
+ num -= den;
+ res |= bit;
+ }
+ bit >>= 1;
+ den >>= 1;
+ }
+ if (modwanted)
+ return num;
+ return res;
+}
+
+
+
+SItype
+__divsi3 (SItype a, SItype b)
+{
+ word_type neg = 0;
+ SItype res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0)
+ {
+ b = -b;
+ neg = !neg;
+ }
+
+ res = udivmodsi4 (a, b, 0);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+
+
+SItype
+__modsi3 (SItype a, SItype b)
+{
+ word_type neg = 0;
+ SItype res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+ res = udivmodsi4 (a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+
+
+
+SItype
+__udivsi3 (SItype a, SItype b)
+{
+ return udivmodsi4 (a, b, 0);
+}
+
+
+
+SItype
+__umodsi3 (SItype a, SItype b)
+{
+ return udivmodsi4 (a, b, 1);
+}
--- /dev/null
+/* Target-Specific Modes for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+/* 24-bit pointers, whole */
+/*INT_MODE (PI, 3);*/
+
+/* 24-bit pointers, in 32-bit units */
+PARTIAL_INT_MODE (SI);
+
+/* 48-bit MULEX result */
+/* INT_MODE (MI, 6); */
--- /dev/null
+/* M32C Pragma support
+ Copyright (C) 2004 Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include <stdio.h>
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "toplev.h"
+#include "c-pragma.h"
+#include "cpplib.h"
+#include "hard-reg-set.h"
+#include "output.h"
+#include "m32c-protos.h"
+#include "function.h"
+#define MAX_RECOG_OPERANDS 10
+#include "reload.h"
+#include "target.h"
+
+/* Implements the "GCC memregs" pragma. This pragma takes only an
+ integer, and is semantically identical to the -memregs= command
+ line option. The only catch is, the programmer should only use
+ this pragma at the beginning of the file (preferably, in some
+ project-wide header) to avoid ABI changes related to changing the
+ list of available "registers". */
+static void
+m32c_pragma_memregs (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+ /* on off */
+ tree val;
+ enum cpp_ttype type;
+ HOST_WIDE_INT i;
+ static char new_number[3];
+
+ type = c_lex (&val);
+ if (type == CPP_NUMBER)
+ {
+ if (host_integerp (val, 1))
+ {
+ i = tree_low_cst (val, 1);
+
+ type = c_lex (&val);
+ if (type != CPP_EOF)
+ warning (0, "junk at end of #pragma GCC memregs [0..16]");
+
+ if (0 <= i && i <= 16)
+ {
+ if (!ok_to_change_target_memregs)
+ {
+ warning (0,
+ "#pragma GCC memregs must precede any function decls");
+ return;
+ }
+ new_number[0] = (i / 10) + '0';
+ new_number[1] = (i % 10) + '0';
+ new_number[2] = 0;
+ target_memregs = new_number;
+ m32c_conditional_register_usage ();
+ }
+ else
+ {
+ warning (0, "#pragma GCC memregs takes a number [0..16]");
+ }
+
+ return;
+ }
+ }
+
+ error ("#pragma GCC memregs takes a number [0..16]");
+}
+
+/* Implements REGISTER_TARGET_PRAGMAS. */
+void
+m32c_register_pragmas (void)
+{
+ c_register_pragma ("GCC", "memregs", m32c_pragma_memregs);
+}
--- /dev/null
+/* Target Prototypes for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define MM enum machine_mode
+#define UINT unsigned int
+
+int m32c_class_likely_spilled_p (int);
+void m32c_conditional_register_usage (void);
+int m32c_const_ok_for_constraint_p (HOST_WIDE_INT, char, const char *);
+UINT m32c_dwarf_frame_regnum (int);
+int m32c_eh_return_data_regno (int);
+void m32c_emit_epilogue (void);
+void m32c_emit_prologue (void);
+int m32c_epilogue_uses (int);
+int m32c_extra_address_constraint (char, const char *);
+int m32c_extra_memory_constraint (char, const char *);
+int m32c_function_arg_regno_p (int);
+void m32c_init_expanders (void);
+int m32c_initial_elimination_offset (int, int);
+void m32c_output_reg_pop (FILE *, int);
+void m32c_output_reg_push (FILE *, int);
+void m32c_override_options (void);
+int m32c_print_operand_punct_valid_p (int);
+int m32c_push_rounding (int);
+int m32c_reg_class_from_constraint (char, const char *);
+void m32c_register_pragmas (void);
+int m32c_regno_ok_for_base_p (int);
+int m32c_trampoline_alignment (void);
+int m32c_trampoline_size (void);
+
+#if defined(RTX_CODE) && defined(TREE_CODE)
+
+rtx m32c_function_arg (CUMULATIVE_ARGS *, MM, tree, int);
+rtx m32c_function_value (tree, tree);
+
+#endif
+
+#ifdef RTX_CODE
+
+int m32c_cannot_change_mode_class (MM, MM, int);
+int m32c_class_max_nregs (int, MM);
+rtx m32c_eh_return_stackadj_rtx (void);
+void m32c_emit_eh_epilogue (rtx);
+int m32c_extra_constraint_p (rtx, char, const char *);
+int m32c_extra_constraint_p2 (rtx, char, const char *);
+int m32c_hard_regno_nregs (int, MM);
+int m32c_hard_regno_ok (int, MM);
+rtx m32c_incoming_return_addr_rtx (void);
+void m32c_initialize_trampoline (rtx, rtx, rtx);
+int m32c_legitimate_address_p (MM, rtx, int);
+int m32c_legitimate_constant_p (rtx);
+int m32c_legitimize_address (rtx *, rtx, MM);
+int m32c_legitimize_reload_address (rtx *, MM, int, int, int);
+rtx m32c_libcall_value (MM);
+int m32c_limit_reload_class (MM, int);
+int m32c_memory_move_cost (MM, int, int);
+int m32c_mode_dependent_address (rtx);
+int m32c_modes_tieable_p (MM, MM);
+bool m32c_mov_ok (rtx *, MM);
+int m32c_preferred_output_reload_class (rtx, int);
+int m32c_preferred_reload_class (rtx, int);
+int m32c_prepare_move (rtx *, MM);
+int m32c_prepare_shift (rtx *, int, int);
+void m32c_print_operand (FILE *, rtx, int);
+void m32c_print_operand_address (FILE *, rtx);
+int m32c_reg_ok_for_base_p (rtx, int);
+int m32c_register_move_cost (MM, int, int);
+MM m32c_regno_reg_class (int);
+rtx m32c_return_addr_rtx (int);
+int m32c_secondary_reload_class (int, MM, rtx);
+int m32c_split_move (rtx *, MM, int);
+int m32c_split_psi_p (rtx *);
+
+#endif
+
+#ifdef TREE_CODE
+
+void m32c_function_arg_advance (CUMULATIVE_ARGS *, MM, tree, int);
+tree m32c_gimplify_va_arg_expr (tree, tree, tree *, tree *);
+void m32c_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+bool m32c_promote_function_return (tree);
+
+#endif
+
+#undef MM
+#undef UINT
--- /dev/null
+ Target Definitions for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
+
+
+These are just some random notes I used during development of this
+port. Please don't consider these to be "official" specifications,
+just additional information to help make the code easier to
+understand.
+
+
+Frame
+=====
+
+ +--------------------
+ | incoming args
+ +--------------------
+ | return Address
+osp -> +--------------------
+ | saved fp
+fp -> +--------------------
+ | local data
+ +--------------------
+ | saved regs
+ +--------------------
+ | outgoing args (opt)
+sp -> +--------------------
+
+Argument Passing
+================
+
+r8c, m16c
+---------
+
+First arg may be passed in r1l or r1 if it (1) fits (QImode or
+HImode), (2) is named, and (3) is an integer or pointer type (no
+structs, floats, etc). Otherwise, it's passed on the stack.
+
+Second arg may be passed in r2, same restrictions (but not QImode),
+even if the first arg is passed on the stack.
+
+Third and further args are passed on the stack. No padding is used,
+stack "alignment" is 8 bits.
+
+m32cm, m32c
+-----------
+First arg may be passed in r0l or r0, same restrictions as above.
+
+Second and further args are passed on the stack. Padding is used
+after QImode parameters (i.e. lower-addressed byte is the value,
+higher-addressed byte is the padding), stack "alignment" is 16 bits.
+
+
+Return Value
+============
+
+r8c, m16c
+---------
+
+QImode in r0l
+HImode in r0
+near pointer in r0
+(desired)
+SImode in r2r0
+far pointer in r2r0
+(actual)
+Anything bigger than 16 bits is returned in memory, at mem0 (mem0
+through mem15 are provided by libgcc.a)
+
+Aggregate values (regardless of size) are returned by pushing a
+pointer to a temporary area on the stack after the args are pushed.
+The function fills in this area with the value. Note that this
+pointer on the stack does not affect how register arguments, if any,
+are configured.
+
+m32cm, m32c
+-----------
+Same.
+
+
+Registers Preserved Across Calls
+================================
+
+r8c, m16c
+---------
+sb, fb, sp (i.e. nearly all registers are call clobbered)
+
+m32cm, m32c
+-----------
+r1, r2, r3, a0, a1, sb, fb, sp
+(except when used for return values)
+
+
+Interrupt Handlers
+==================
+
+The stack frame is slightly different for interrupt handlers, because
+(1) we don't have a usable parent frame, and (2) we have to use
+special instructions to return and thus must save/restore everything
+differently.
+
+ +--------------------
+ | program state
+osp -> +--------------------
+ | return address
+ +--------------------
+ | saved r0..fp (pushm)
+fp -> +--------------------
+ | local data
+ +--------------------
+ | saved regs mem0..mem15
+ +--------------------
+ | outgoing args (opt)
+sp -> +--------------------
+
--- /dev/null
+/* Target Code for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "reload.h"
+#include "toplev.h"
+#include "obstack.h"
+#include "tree.h"
+#include "expr.h"
+#include "optabs.h"
+#include "except.h"
+#include "function.h"
+#include "ggc.h"
+#include "target.h"
+#include "target-def.h"
+#include "tm_p.h"
+#include "langhooks.h"
+#include "tree-gimple.h"
+
+/* Prototypes */
+
+/* Used by m32c_pushm_popm. */
+typedef enum
+{
+ PP_pushm,
+ PP_popm,
+ PP_justcount
+} Push_Pop_Type;
+
+static tree interrupt_handler (tree *, tree, tree, int, bool *);
+static int interrupt_p (tree node);
+static bool m32c_asm_integer (rtx, unsigned int, int);
+static int m32c_comp_type_attributes (tree, tree);
+static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
+static struct machine_function *m32c_init_machine_status (void);
+static void m32c_insert_attributes (tree, tree *);
+static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
+ tree, bool);
+static bool m32c_promote_prototypes (tree);
+static int m32c_pushm_popm (Push_Pop_Type);
+static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
+static rtx m32c_struct_value_rtx (tree, int);
+static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
+static int need_to_save (int);
+
+#define streq(a,b) (strcmp ((a), (b)) == 0)
+
+/* Internal support routines */
+
+/* Debugging statements are tagged with DEBUG0 only so that they can
+ be easily enabled individually, by replacing the '0' with '1' as
+ needed. */
+#define DEBUG0 0
+#define DEBUG1 1
+
+#if DEBUG0
+/* This is needed by some of the commented-out debug statements
+ below. */
+static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
+#endif
+static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
+
+/* These are all to support encode_pattern(). */
+static char pattern[30], *patternp;
+static GTY(()) rtx patternr[30];
+#define RTX_IS(x) (streq (pattern, x))
+
+/* Some macros to simplify the logic throughout this file. */
+#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
+#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
+
+#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
+#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
+
+/* We do most RTX matching by converting the RTX into a string, and
+ using string compares. This vastly simplifies the logic in many of
+ the functions in this file.
+
+ On exit, pattern[] has the encoded string (use RTX_IS("...") to
+ compare it) and patternr[] has pointers to the nodes in the RTX
+ corresponding to each character in the encoded string. The latter
+ is mostly used by print_operand().
+
+ Unrecognized patterns have '?' in them; this shows up when the
+ assembler complains about syntax errors.
+*/
+
+static void
+encode_pattern_1 (rtx x)
+{
+ int i;
+
+ if (patternp == pattern + sizeof (pattern) - 2)
+ {
+ patternp[-1] = '?';
+ return;
+ }
+
+ patternr[patternp - pattern] = x;
+
+ switch (GET_CODE (x))
+ {
+ case REG:
+ *patternp++ = 'r';
+ break;
+ case SUBREG:
+ if (GET_MODE_SIZE (GET_MODE (x)) !=
+ GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
+ *patternp++ = 'S';
+ encode_pattern_1 (XEXP (x, 0));
+ break;
+ case MEM:
+ *patternp++ = 'm';
+ case CONST:
+ encode_pattern_1 (XEXP (x, 0));
+ break;
+ case PLUS:
+ *patternp++ = '+';
+ encode_pattern_1 (XEXP (x, 0));
+ encode_pattern_1 (XEXP (x, 1));
+ break;
+ case PRE_DEC:
+ *patternp++ = '>';
+ encode_pattern_1 (XEXP (x, 0));
+ break;
+ case POST_INC:
+ *patternp++ = '<';
+ encode_pattern_1 (XEXP (x, 0));
+ break;
+ case LO_SUM:
+ *patternp++ = 'L';
+ encode_pattern_1 (XEXP (x, 0));
+ encode_pattern_1 (XEXP (x, 1));
+ break;
+ case HIGH:
+ *patternp++ = 'H';
+ encode_pattern_1 (XEXP (x, 0));
+ break;
+ case SYMBOL_REF:
+ *patternp++ = 's';
+ break;
+ case LABEL_REF:
+ *patternp++ = 'l';
+ break;
+ case CODE_LABEL:
+ *patternp++ = 'c';
+ break;
+ case CONST_INT:
+ case CONST_DOUBLE:
+ *patternp++ = 'i';
+ break;
+ case UNSPEC:
+ *patternp++ = 'u';
+ *patternp++ = '0' + XCINT (x, 1, UNSPEC);
+ for (i = 0; i < XVECLEN (x, 0); i++)
+ encode_pattern_1 (XVECEXP (x, 0, i));
+ break;
+ case USE:
+ *patternp++ = 'U';
+ break;
+ case PARALLEL:
+ *patternp++ = '|';
+ for (i = 0; i < XVECLEN (x, 0); i++)
+ encode_pattern_1 (XVECEXP (x, 0, i));
+ break;
+ case EXPR_LIST:
+ *patternp++ = 'E';
+ encode_pattern_1 (XEXP (x, 0));
+ if (XEXP (x, 1))
+ encode_pattern_1 (XEXP (x, 1));
+ break;
+ default:
+ *patternp++ = '?';
+#if DEBUG0
+ fprintf (stderr, "can't encode pattern %s\n",
+ GET_RTX_NAME (GET_CODE (x)));
+ debug_rtx (x);
+ gcc_unreachable ();
+#endif
+ break;
+ }
+}
+
+static void
+encode_pattern (rtx x)
+{
+ patternp = pattern;
+ encode_pattern_1 (x);
+ *patternp = 0;
+}
+
+/* Since register names indicate the mode they're used in, we need a
+ way to determine which name to refer to the register with. Called
+ by print_operand(). */
+
+static const char *
+reg_name_with_mode (int regno, enum machine_mode mode)
+{
+ int mlen = GET_MODE_SIZE (mode);
+ if (regno == R0_REGNO && mlen == 1)
+ return "r0l";
+ if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
+ return "r2r0";
+ if (regno == R0_REGNO && mlen == 6)
+ return "r2r1r0";
+ if (regno == R0_REGNO && mlen == 8)
+ return "r3r1r2r0";
+ if (regno == R1_REGNO && mlen == 1)
+ return "r1l";
+ if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
+ return "r3r1";
+ if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
+ return "a1a0";
+ return reg_names[regno];
+}
+
+/* How many bytes a register uses on stack when it's pushed. We need
+ to know this because the push opcode needs to explicitly indicate
+ the size of the register, even though the name of the register
+ already tells it that. Used by m32c_output_reg_{push,pop}, which
+ is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
+
+static int
+reg_push_size (int regno)
+{
+ switch (regno)
+ {
+ case R0_REGNO:
+ case R1_REGNO:
+ return 2;
+ case R2_REGNO:
+ case R3_REGNO:
+ case FLG_REGNO:
+ return 2;
+ case A0_REGNO:
+ case A1_REGNO:
+ case SB_REGNO:
+ case FB_REGNO:
+ case SP_REGNO:
+ if (TARGET_A16)
+ return 2;
+ else
+ return 3;
+ default:
+ gcc_unreachable ();
+ }
+}
+
+static int *class_sizes = 0;
+
+/* Given two register classes, find the largest intersection between
+ them. If there is no intersection, return RETURNED_IF_EMPTY
+ instead. */
+static int
+reduce_class (int original_class, int limiting_class, int returned_if_empty)
+{
+ int cc = class_contents[original_class][0];
+ int i, best = NO_REGS;
+ int best_size = 0;
+
+ if (original_class == limiting_class)
+ return original_class;
+
+ if (!class_sizes)
+ {
+ int r;
+ class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
+ for (i = 0; i < LIM_REG_CLASSES; i++)
+ {
+ class_sizes[i] = 0;
+ for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+ if (class_contents[i][0] & (1 << r))
+ class_sizes[i]++;
+ }
+ }
+
+ cc &= class_contents[limiting_class][0];
+ for (i = 0; i < LIM_REG_CLASSES; i++)
+ {
+ int ic = class_contents[i][0];
+
+ if ((~cc & ic) == 0)
+ if (best_size < class_sizes[i])
+ {
+ best = i;
+ best_size = class_sizes[i];
+ }
+
+ }
+ if (best == NO_REGS)
+ return returned_if_empty;
+ return best;
+}
+
+/* Returns TRUE If there are any registers that exist in both register
+ classes. */
+static int
+classes_intersect (int class1, int class2)
+{
+ return class_contents[class1][0] & class_contents[class2][0];
+}
+
+/* Used by m32c_register_move_cost to determine if a move is
+ impossibly expensive. */
+static int
+class_can_hold_mode (int class, enum machine_mode mode)
+{
+ /* Cache the results: 0=untested 1=no 2=yes */
+ static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
+ if (results[class][mode] == 0)
+ {
+ int r, n, i;
+ results[class][mode] = 1;
+ for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+ if (class_contents[class][0] & (1 << r)
+ && HARD_REGNO_MODE_OK (r, mode))
+ {
+ int ok = 1;
+ n = HARD_REGNO_NREGS (r, mode);
+ for (i = 1; i < n; i++)
+ if (!(class_contents[class][0] & (1 << (r + i))))
+ ok = 0;
+ if (ok)
+ {
+ results[class][mode] = 2;
+ break;
+ }
+ }
+ }
+#if DEBUG0
+ fprintf (stderr, "class %s can hold %s? %s\n",
+ class_names[class], mode_name[mode],
+ (results[class][mode] == 2) ? "yes" : "no");
+#endif
+ return results[class][mode] == 2;
+}
+
+/* Run-time Target Specification. */
+
+/* Memregs are memory locations that gcc treats like general
+ registers, as there are a limited number of true registers and the
+ m32c families can use memory in most places that registers can be
+ used.
+
+ However, since memory accesses are more expensive than registers,
+ we allow the user to limit the number of memregs available, in
+ order to try to persuade gcc to try harder to use real registers.
+
+ Memregs are provided by m32c-lib1.S.
+*/
+
+int target_memregs = 16;
+static bool target_memregs_set = FALSE;
+int ok_to_change_target_memregs = TRUE;
+
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION m32c_handle_option
+static bool
+m32c_handle_option (size_t code,
+ const char *arg ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED)
+{
+ if (code == OPT_memregs_)
+ {
+ target_memregs_set = TRUE;
+ target_memregs = atoi (arg);
+ }
+ return TRUE;
+}
+
+/* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
+ provide a default. */
+void
+m32c_override_options (void)
+{
+ if (target_memregs_set)
+ {
+ if (target_memregs < 0 || target_memregs > 16)
+ error ("invalid target memregs value '%d'", target_memregs);
+ }
+ else
+ target_memregs = "16";
+}
+
+/* Defining data structures for per-function information */
+
+/* The usual; we set up our machine_function data. */
+static struct machine_function *
+m32c_init_machine_status (void)
+{
+ struct machine_function *machine;
+ machine =
+ (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
+
+ return machine;
+}
+
+/* Implements INIT_EXPANDERS. We just set up to call the above
+ function. */
+void
+m32c_init_expanders (void)
+{
+ init_machine_status = m32c_init_machine_status;
+}
+
+/* Storage Layout */
+
+#undef TARGET_PROMOTE_FUNCTION_RETURN
+#define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
+bool
+m32c_promote_function_return (tree fntype ATTRIBUTE_UNUSED)
+{
+ return false;
+}
+
+/* Register Basics */
+
+/* Basic Characteristics of Registers */
+
+/* Whether a mode fits in a register is complex enough to warrant a
+ table. */
+static struct
+{
+ char qi_regs;
+ char hi_regs;
+ char pi_regs;
+ char si_regs;
+ char di_regs;
+} nregs_table[FIRST_PSEUDO_REGISTER] =
+{
+ { 1, 1, 2, 2, 4 }, /* r0 */
+ { 0, 1, 0, 0, 0 }, /* r2 */
+ { 1, 1, 2, 2, 0 }, /* r1 */
+ { 0, 1, 0, 0, 0 }, /* r3 */
+ { 0, 1, 1, 0, 0 }, /* a0 */
+ { 0, 1, 1, 0, 0 }, /* a1 */
+ { 0, 1, 1, 0, 0 }, /* sb */
+ { 0, 1, 1, 0, 0 }, /* fb */
+ { 0, 1, 1, 0, 0 }, /* sp */
+ { 1, 1, 1, 0, 0 }, /* pc */
+ { 0, 0, 0, 0, 0 }, /* fl */
+ { 1, 1, 1, 0, 0 }, /* ap */
+ { 1, 1, 2, 2, 4 }, /* mem0 */
+ { 1, 1, 2, 2, 4 }, /* mem1 */
+ { 1, 1, 2, 2, 4 }, /* mem2 */
+ { 1, 1, 2, 2, 4 }, /* mem3 */
+ { 1, 1, 2, 2, 4 }, /* mem4 */
+ { 1, 1, 2, 2, 0 }, /* mem5 */
+ { 1, 1, 2, 2, 0 }, /* mem6 */
+ { 1, 1, 0, 0, 0 }, /* mem7 */
+};
+
+/* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
+ available memregs, and select which registers need to be preserved
+ across calls based on the chip family. */
+
+void
+m32c_conditional_register_usage (void)
+{
+ int memregs;
+ int i;
+
+ if (0 <= target_memregs && target_memregs <= 16)
+ {
+ /* The command line option is bytes, but our "registers" are
+ 16-bit words. */
+ for (i = target_memregs/2; i < 8; i++)
+ {
+ fixed_regs[MEM0_REGNO + i] = 1;
+ CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
+ }
+ }
+
+ /* M32CM and M32C preserve more registers across function calls. */
+ if (TARGET_A24)
+ {
+ call_used_regs[R1_REGNO] = 0;
+ call_used_regs[R2_REGNO] = 0;
+ call_used_regs[R3_REGNO] = 0;
+ call_used_regs[A0_REGNO] = 0;
+ call_used_regs[A1_REGNO] = 0;
+ }
+}
+
+/* How Values Fit in Registers */
+
+/* Implements HARD_REGNO_NREGS. This is complicated by the fact that
+ different registers are different sizes from each other, *and* may
+ be different sizes in different chip families. */
+int
+m32c_hard_regno_nregs (int regno, enum machine_mode mode)
+{
+ if (regno == FLG_REGNO && mode == CCmode)
+ return 1;
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
+
+ if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
+ return (GET_MODE_SIZE (mode) + 1) / 2;
+
+ if (GET_MODE_SIZE (mode) <= 1)
+ return nregs_table[regno].qi_regs;
+ if (GET_MODE_SIZE (mode) <= 2)
+ return nregs_table[regno].hi_regs;
+ if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
+ return 2;
+ if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
+ return nregs_table[regno].pi_regs;
+ if (GET_MODE_SIZE (mode) <= 4)
+ return nregs_table[regno].si_regs;
+ if (GET_MODE_SIZE (mode) <= 8)
+ return nregs_table[regno].di_regs;
+ return 0;
+}
+
+/* Implements HARD_REGNO_MODE_OK. The above function does the work
+ already; just test its return value. */
+int
+m32c_hard_regno_ok (int regno, enum machine_mode mode)
+{
+ return m32c_hard_regno_nregs (regno, mode) != 0;
+}
+
+/* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
+ registers are all different sizes. However, since most modes are
+ bigger than our registers anyway, it's easier to implement this
+ function that way, leaving QImode as the only unique case. */
+int
+m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
+{
+ if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
+ return 1;
+
+ if (m1 == QImode || m2 == QImode)
+ return 0;
+
+ return 1;
+}
+
+/* Register Classes */
+
+/* Implements REGNO_REG_CLASS. */
+enum machine_mode
+m32c_regno_reg_class (int regno)
+{
+ switch (regno)
+ {
+ case R0_REGNO:
+ return R0_REGS;
+ case R1_REGNO:
+ return R1_REGS;
+ case R2_REGNO:
+ return R2_REGS;
+ case R3_REGNO:
+ return R3_REGS;
+ case A0_REGNO:
+ case A1_REGNO:
+ return A_REGS;
+ case SB_REGNO:
+ return SB_REGS;
+ case FB_REGNO:
+ return FB_REGS;
+ case SP_REGNO:
+ return SP_REGS;
+ case FLG_REGNO:
+ return FLG_REGS;
+ default:
+ if (IS_MEM_REGNO (regno))
+ return MEM_REGS;
+ return ALL_REGS;
+ }
+}
+
+/* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
+ for certain chip families. */
+int
+m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
+{
+ if (memcmp (s, "Rsp", 3) == 0)
+ return SP_REGS;
+ if (memcmp (s, "Rfb", 3) == 0)
+ return FB_REGS;
+ if (memcmp (s, "Rsb", 3) == 0)
+ return SB_REGS;
+ if (memcmp (s, "Rcr", 3) == 0 && TARGET_A16)
+ return CR_REGS;
+ if (memcmp (s, "Rcl", 3) == 0 && TARGET_A24)
+ return CR_REGS;
+ if (memcmp (s, "R0w", 3) == 0)
+ return R0_REGS;
+ if (memcmp (s, "R1w", 3) == 0)
+ return R1_REGS;
+ if (memcmp (s, "R2w", 3) == 0)
+ return R2_REGS;
+ if (memcmp (s, "R3w", 3) == 0)
+ return R3_REGS;
+ if (memcmp (s, "R02", 3) == 0)
+ return R02_REGS;
+ if (memcmp (s, "R03", 3) == 0)
+ return R03_REGS;
+ if (memcmp (s, "Rdi", 3) == 0)
+ return DI_REGS;
+ if (memcmp (s, "Rhl", 3) == 0)
+ return HL_REGS;
+ if (memcmp (s, "R23", 3) == 0)
+ return R23_REGS;
+ if (memcmp (s, "Raa", 3) == 0)
+ return A_REGS;
+ if (memcmp (s, "Raw", 3) == 0 && TARGET_A16)
+ return A_REGS;
+ if (memcmp (s, "Ral", 3) == 0 && TARGET_A24)
+ return A_REGS;
+ if (memcmp (s, "Rqi", 3) == 0)
+ return QI_REGS;
+ if (memcmp (s, "Rad", 3) == 0)
+ return AD_REGS;
+ if (memcmp (s, "Rsi", 3) == 0)
+ return SI_REGS;
+ if (memcmp (s, "Rhi", 3) == 0)
+ return HI_REGS;
+ if (memcmp (s, "Rhc", 3) == 0)
+ return HC_REGS;
+ if (memcmp (s, "Rra", 3) == 0)
+ return RA_REGS;
+ if (memcmp (s, "Rfl", 3) == 0)
+ return FLG_REGS;
+ if (memcmp (s, "Rmm", 3) == 0)
+ {
+ if (fixed_regs[MEM0_REGNO])
+ return NO_REGS;
+ return MEM_REGS;
+ }
+
+ /* PSImode registers - i.e. whatever can hold a pointer. */
+ if (memcmp (s, "Rpi", 3) == 0)
+ {
+ if (TARGET_A16)
+ return HI_REGS;
+ else
+ return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
+ }
+
+ /* We handle this one as an EXTRA_CONSTRAINT. */
+ if (memcmp (s, "Rpa", 3) == 0)
+ return NO_REGS;
+
+ return NO_REGS;
+}
+
+/* Implements REGNO_OK_FOR_BASE_P. */
+int
+m32c_regno_ok_for_base_p (int regno)
+{
+ if (regno == A0_REGNO
+ || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
+ return 1;
+ return 0;
+}
+
+#define DEBUG_RELOAD 0
+
+/* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
+ registers of the appropriate size. */
+int
+m32c_preferred_reload_class (rtx x, int rclass)
+{
+ int newclass = rclass;
+
+#if DEBUG_RELOAD
+ fprintf (stderr, "\npreferred_reload_class for %s is ",
+ class_names[rclass]);
+#endif
+ if (rclass == NO_REGS)
+ rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
+
+ if (classes_intersect (rclass, CR_REGS))
+ {
+ switch (GET_MODE (x))
+ {
+ case QImode:
+ newclass = HL_REGS;
+ break;
+ default:
+ /* newclass = HI_REGS; */
+ break;
+ }
+ }
+
+ else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
+ newclass = SI_REGS;
+ else if (GET_MODE_SIZE (GET_MODE (x)) > 4
+ && ~class_contents[rclass][0] & 0x000f)
+ newclass = DI_REGS;
+
+ rclass = reduce_class (rclass, newclass, rclass);
+
+ if (GET_MODE (x) == QImode)
+ rclass = reduce_class (rclass, HL_REGS, rclass);
+
+#if DEBUG_RELOAD
+ fprintf (stderr, "%s\n", class_names[rclass]);
+ debug_rtx (x);
+
+ if (GET_CODE (x) == MEM
+ && GET_CODE (XEXP (x, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
+ fprintf (stderr, "Glorm!\n");
+#endif
+ return rclass;
+}
+
+/* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
+int
+m32c_preferred_output_reload_class (rtx x, int rclass)
+{
+ return m32c_preferred_reload_class (x, rclass);
+}
+
+/* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
+ address registers for reloads since they're needed for address
+ reloads. */
+int
+m32c_limit_reload_class (enum machine_mode mode, int rclass)
+{
+#if DEBUG_RELOAD
+ fprintf (stderr, "limit_reload_class for %s: %s ->",
+ mode_name[mode], class_names[rclass]);
+#endif
+
+ if (mode == QImode)
+ rclass = reduce_class (rclass, HL_REGS, rclass);
+ else if (mode == HImode)
+ rclass = reduce_class (rclass, HI_REGS, rclass);
+ else if (mode == SImode)
+ rclass = reduce_class (rclass, SI_REGS, rclass);
+
+ if (rclass != A_REGS)
+ rclass = reduce_class (rclass, DI_REGS, rclass);
+
+#if DEBUG_RELOAD
+ fprintf (stderr, " %s\n", class_names[rclass]);
+#endif
+ return rclass;
+}
+
+/* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
+ r0 or r1, as those are the only real QImode registers. CR regs get
+ reloaded through appropriately sized general or address
+ registers. */
+int
+m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
+{
+ int cc = class_contents[rclass][0];
+#if DEBUG0
+ fprintf (stderr, "\nsecondary reload class %s %s\n",
+ class_names[rclass], mode_name[mode]);
+ debug_rtx (x);
+#endif
+ if (mode == QImode
+ && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
+ return QI_REGS;
+ if (classes_intersect (rclass, CR_REGS)
+ && GET_CODE (x) == REG
+ && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
+ return TARGET_A16 ? HI_REGS : A_REGS;
+ return NO_REGS;
+}
+
+/* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
+ reloads. */
+int
+m32c_class_likely_spilled_p (int regclass)
+{
+ if (regclass == A_REGS)
+ return 1;
+ return reg_class_size[regclass] == 1;
+}
+
+/* Implements CLASS_MAX_NREGS. We calculate this according to its
+ documented meaning, to avoid potential inconsistencies with actual
+ class definitions. */
+int
+m32c_class_max_nregs (int regclass, enum machine_mode mode)
+{
+ int rn, max = 0;
+
+ for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
+ if (class_contents[regclass][0] & (1 << rn))
+ {
+ int n = m32c_hard_regno_nregs (rn, mode);
+ if (max < n)
+ max = n;
+ }
+ return max;
+}
+
+/* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
+ QI (r0l, r1l) because the chip doesn't support QI ops on other
+ registers (well, it does on a0/a1 but if we let gcc do that, reload
+ suffers). Otherwise, we allow changes to larger modes. */
+int
+m32c_cannot_change_mode_class (enum machine_mode from,
+ enum machine_mode to, int rclass)
+{
+#if DEBUG0
+ fprintf (stderr, "cannot change from %s to %s in %s\n",
+ mode_name[from], mode_name[to], class_names[rclass]);
+#endif
+
+ if (to == QImode)
+ return (class_contents[rclass][0] & 0x1ffa);
+
+ if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
+ && GET_MODE_SIZE (from) > 1)
+ return 0;
+ if (GET_MODE_SIZE (from) > 2) /* all other regs */
+ return 0;
+
+ return 1;
+}
+
+/* Helpers for the rest of the file. */
+/* TRUE if the rtx is a REG rtx for the given register. */
+#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
+ && REGNO (rtx) == regno)
+/* TRUE if the rtx is a pseudo - specifically, one we can use as a
+ base register in address calculations (hence the "strict"
+ argument). */
+#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
+ && (REGNO (rtx) == AP_REGNO \
+ || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
+
+/* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
+ constraints start with 'I', with the next two characters indicating
+ the type and size of the range allowed. */
+int
+m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
+ char c ATTRIBUTE_UNUSED, const char *str)
+{
+ /* s=signed u=unsigned n=nonzero m=minus l=log2able,
+ [sun] bits [SUN] bytes, p=pointer size
+ I[-0-9][0-9] matches that number */
+ if (memcmp (str, "Is3", 3) == 0)
+ {
+ return (-8 <= value && value <= 7);
+ }
+ if (memcmp (str, "IS1", 3) == 0)
+ {
+ return (-128 <= value && value <= 127);
+ }
+ if (memcmp (str, "IS2", 3) == 0)
+ {
+ return (-32768 <= value && value <= 32767);
+ }
+ if (memcmp (str, "IU2", 3) == 0)
+ {
+ return (0 <= value && value <= 65535);
+ }
+ if (memcmp (str, "IU3", 3) == 0)
+ {
+ return (0 <= value && value <= 0x00ffffff);
+ }
+ if (memcmp (str, "In4", 3) == 0)
+ {
+ return (-8 <= value && value && value <= 8);
+ }
+ if (memcmp (str, "In5", 3) == 0)
+ {
+ return (-16 <= value && value && value <= 16);
+ }
+ if (memcmp (str, "IM2", 3) == 0)
+ {
+ return (-65536 <= value && value && value <= -1);
+ }
+ if (memcmp (str, "Ilb", 3) == 0)
+ {
+ int b = exact_log2 (value);
+ return (b >= 1 && b <= 8);
+ }
+ if (memcmp (str, "Ilw", 3) == 0)
+ {
+ int b = exact_log2 (value);
+ return (b >= 1 && b <= 16);
+ }
+ return 0;
+}
+
+/* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
+ for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
+ call return values. */
+int
+m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
+{
+ encode_pattern (value);
+ if (memcmp (str, "Sd", 2) == 0)
+ {
+ /* This is the common "src/dest" address */
+ rtx r;
+ if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
+ return 1;
+ if (RTX_IS ("ms") || RTX_IS ("m+si"))
+ return 1;
+ if (RTX_IS ("mr"))
+ r = patternr[1];
+ else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
+ r = patternr[2];
+ else
+ return 0;
+ if (REGNO (r) == SP_REGNO)
+ return 0;
+ return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
+ }
+ else if (memcmp (str, "Sa", 2) == 0)
+ {
+ rtx r;
+ if (RTX_IS ("mr"))
+ r = patternr[1];
+ else if (RTX_IS ("m+ri"))
+ r = patternr[2];
+ else
+ return 0;
+ return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
+ }
+ else if (memcmp (str, "Si", 2) == 0)
+ {
+ return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
+ }
+ else if (memcmp (str, "Ss", 2) == 0)
+ {
+ return ((RTX_IS ("mr")
+ && (IS_REG (patternr[1], SP_REGNO)))
+ || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
+ }
+ else if (memcmp (str, "Sf", 2) == 0)
+ {
+ return ((RTX_IS ("mr")
+ && (IS_REG (patternr[1], FB_REGNO)))
+ || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
+ }
+ else if (memcmp (str, "Sb", 2) == 0)
+ {
+ return ((RTX_IS ("mr")
+ && (IS_REG (patternr[1], SB_REGNO)))
+ || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
+ }
+ else if (memcmp (str, "S1", 2) == 0)
+ {
+ return r1h_operand (value, QImode);
+ }
+
+ gcc_assert (str[0] != 'S');
+
+ if (memcmp (str, "Rpa", 2) == 0)
+ return GET_CODE (value) == PARALLEL;
+
+ return 0;
+}
+
+/* This is for when we're debugging the above. */
+int
+m32c_extra_constraint_p (rtx value, char c, const char *str)
+{
+ int rv = m32c_extra_constraint_p2 (value, c, str);
+#if DEBUG0
+ fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
+ rv);
+ debug_rtx (value);
+#endif
+ return rv;
+}
+
+/* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
+ starting with 'S'. */
+int
+m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
+{
+ return c == 'S';
+}
+
+/* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
+ but don't currently define any. */
+int
+m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
+{
+ return c == 'A';
+}
+
+/* STACK AND CALLING */
+
+/* Frame Layout */
+
+/* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
+ (yes, THREE bytes) onto the stack for the return address, but we
+ don't support pointers bigger than 16 bits on those chips. This
+ will likely wreak havoc with exception unwinding. FIXME. */
+rtx
+m32c_return_addr_rtx (int count)
+{
+ enum machine_mode mode;
+ int offset;
+ rtx ra_mem;
+
+ if (count)
+ return NULL_RTX;
+ /* we want 2[$fb] */
+
+ if (TARGET_A24)
+ {
+ mode = SImode;
+ offset = 4;
+ }
+ else
+ {
+ /* FIXME: it's really 3 bytes */
+ mode = HImode;
+ offset = 2;
+ }
+
+ ra_mem =
+ gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
+ return copy_to_mode_reg (mode, ra_mem);
+}
+
+/* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
+rtx
+m32c_incoming_return_addr_rtx (void)
+{
+ /* we want [sp] */
+ return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
+}
+
+/* Exception Handling Support */
+
+/* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
+ pointers. */
+int
+m32c_eh_return_data_regno (int n)
+{
+ switch (n)
+ {
+ case 0:
+ return A0_REGNO;
+ case 1:
+ return A1_REGNO;
+ default:
+ return INVALID_REGNUM;
+ }
+}
+
+/* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
+ m32c_emit_eh_epilogue. */
+rtx
+m32c_eh_return_stackadj_rtx (void)
+{
+ if (!cfun->machine->eh_stack_adjust)
+ {
+ rtx sa;
+
+ sa = gen_reg_rtx (Pmode);
+ cfun->machine->eh_stack_adjust = sa;
+ }
+ return cfun->machine->eh_stack_adjust;
+}
+
+/* Registers That Address the Stack Frame */
+
+/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
+ the original spec called for dwarf numbers to vary with register
+ width as well, for example, r0l, r0, and r2r0 would each have
+ different dwarf numbers. GCC doesn't support this, and we don't do
+ it, and gdb seems to like it this way anyway. */
+unsigned int
+m32c_dwarf_frame_regnum (int n)
+{
+ switch (n)
+ {
+ case R0_REGNO:
+ return 5;
+ case R1_REGNO:
+ return 6;
+ case R2_REGNO:
+ return 7;
+ case R3_REGNO:
+ return 8;
+ case A0_REGNO:
+ return 9;
+ case A1_REGNO:
+ return 10;
+ case FB_REGNO:
+ return 11;
+ case SB_REGNO:
+ return 19;
+
+ case SP_REGNO:
+ return 12;
+ case PC_REGNO:
+ return 13;
+ default:
+ return DWARF_FRAME_REGISTERS + 1;
+ }
+}
+
+/* The frame looks like this:
+
+ ap -> +------------------------------
+ | Return address (3 or 4 bytes)
+ | Saved FB (2 or 4 bytes)
+ fb -> +------------------------------
+ | local vars
+ | register saves fb
+ | through r0 as needed
+ sp -> +------------------------------
+*/
+
+/* We use this to wrap all emitted insns in the prologue. */
+static rtx
+F (rtx x)
+{
+ RTX_FRAME_RELATED_P (x) = 1;
+ return x;
+}
+
+/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
+ how much the stack pointer moves for each, for each cpu family. */
+static struct
+{
+ int reg1;
+ int bit;
+ int a16_bytes;
+ int a24_bytes;
+} pushm_info[] =
+{
+ /* These are in push order. */
+ { FB_REGNO, 0x01, 2, 4 },
+ { SB_REGNO, 0x02, 2, 4 },
+ { A1_REGNO, 0x04, 2, 4 },
+ { A0_REGNO, 0x08, 2, 4 },
+ { R3_REGNO, 0x10, 2, 2 },
+ { R2_REGNO, 0x20, 2, 2 },
+ { R1_REGNO, 0x40, 2, 2 },
+ { R0_REGNO, 0x80, 2, 2 }
+};
+
+#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
+
+/* Returns TRUE if we need to save/restore the given register. We
+ save everything for exception handlers, so that any register can be
+ unwound. For interrupt handlers, we save everything if the handler
+ calls something else (because we don't know what *that* function
+ might do), but try to be a bit smarter if the handler is a leaf
+ function. We always save $a0, though, because we use that in the
+ epilog to copy $fb to $sp. */
+static int
+need_to_save (int regno)
+{
+ if (fixed_regs[regno])
+ return 0;
+ if (cfun->calls_eh_return)
+ return 1;
+ if (regno == FP_REGNO)
+ return 0;
+ if (cfun->machine->is_interrupt
+ && (!cfun->machine->is_leaf || regno == A0_REGNO))
+ return 1;
+ if (regs_ever_live[regno]
+ && (!call_used_regs[regno] || cfun->machine->is_interrupt))
+ return 1;
+ return 0;
+}
+
+/* This function contains all the intelligence about saving and
+ restoring registers. It always figures out the register save set.
+ When called with PP_justcount, it merely returns the size of the
+ save set (for eliminating the frame pointer, for example). When
+ called with PP_pushm or PP_popm, it emits the appropriate
+ instructions for saving (pushm) or restoring (popm) the
+ registers. */
+static int
+m32c_pushm_popm (Push_Pop_Type ppt)
+{
+ int reg_mask = 0;
+ int byte_count = 0, bytes;
+ int i;
+ rtx dwarf_set[PUSHM_N];
+ int n_dwarfs = 0;
+ int nosave_mask = 0;
+
+ if (cfun->return_rtx
+ && GET_CODE (cfun->return_rtx) == PARALLEL
+ && !(cfun->calls_eh_return || cfun->machine->is_interrupt))
+ {
+ rtx exp = XVECEXP (cfun->return_rtx, 0, 0);
+ rtx rv = XEXP (exp, 0);
+ int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
+
+ if (rv_bytes > 2)
+ nosave_mask |= 0x20; /* PSI, SI */
+ else
+ nosave_mask |= 0xf0; /* DF */
+ if (rv_bytes > 4)
+ nosave_mask |= 0x50; /* DI */
+ }
+
+ for (i = 0; i < (int) PUSHM_N; i++)
+ {
+ /* Skip if neither register needs saving. */
+ if (!need_to_save (pushm_info[i].reg1))
+ continue;
+
+ if (pushm_info[i].bit & nosave_mask)
+ continue;
+
+ reg_mask |= pushm_info[i].bit;
+ bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
+
+ if (ppt == PP_pushm)
+ {
+ enum machine_mode mode = (bytes == 2) ? HImode : SImode;
+ rtx addr;
+
+ /* Always use stack_pointer_rtx instead of calling
+ rtx_gen_REG ourselves. Code elsewhere in GCC assumes
+ that there is a single rtx representing the stack pointer,
+ namely stack_pointer_rtx, and uses == to recognize it. */
+ addr = stack_pointer_rtx;
+
+ if (byte_count != 0)
+ addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
+
+ dwarf_set[n_dwarfs++] =
+ gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (mode, addr),
+ gen_rtx_REG (mode, pushm_info[i].reg1));
+ F (dwarf_set[n_dwarfs - 1]);
+
+ }
+ byte_count += bytes;
+ }
+
+ if (cfun->machine->is_interrupt)
+ {
+ cfun->machine->intr_pushm = reg_mask & 0xfe;
+ reg_mask = 0;
+ byte_count = 0;
+ }
+
+ if (cfun->machine->is_interrupt)
+ for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
+ if (need_to_save (i))
+ {
+ byte_count += 2;
+ cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
+ }
+
+ if (ppt == PP_pushm && byte_count)
+ {
+ rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
+ rtx pushm;
+
+ if (reg_mask)
+ {
+ XVECEXP (note, 0, 0)
+ = gen_rtx_SET (VOIDmode,
+ stack_pointer_rtx,
+ gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
+ stack_pointer_rtx,
+ GEN_INT (-byte_count)));
+ F (XVECEXP (note, 0, 0));
+
+ for (i = 0; i < n_dwarfs; i++)
+ XVECEXP (note, 0, i + 1) = dwarf_set[i];
+
+ pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
+
+ REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
+ REG_NOTES (pushm));
+ }
+
+ if (cfun->machine->is_interrupt)
+ for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
+ if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
+ {
+ if (TARGET_A16)
+ pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
+ else
+ pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
+ F (pushm);
+ }
+ }
+ if (ppt == PP_popm && byte_count)
+ {
+ rtx insn;
+
+ if (cfun->machine->is_interrupt)
+ for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
+ if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
+ {
+ if (TARGET_A16)
+ insn = emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
+ else
+ insn = emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
+ F (insn);
+ }
+ if (reg_mask)
+ emit_insn (gen_popm (GEN_INT (reg_mask)));
+ }
+
+ return byte_count;
+}
+
+/* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
+ diagrams our call frame. */
+int
+m32c_initial_elimination_offset (int from, int to)
+{
+ int ofs = 0;
+
+ if (from == AP_REGNO)
+ {
+ if (TARGET_A16)
+ ofs += 5;
+ else
+ ofs += 8;
+ }
+
+ if (to == SP_REGNO)
+ {
+ ofs += m32c_pushm_popm (PP_justcount);
+ ofs += get_frame_size ();
+ }
+
+ /* Account for push rounding. */
+ if (TARGET_A24)
+ ofs = (ofs + 1) & ~1;
+#if DEBUG0
+ fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
+ to, ofs);
+#endif
+ return ofs;
+}
+
+/* Passing Function Arguments on the Stack */
+
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
+static bool
+m32c_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+/* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
+ M32C has word stacks. */
+int
+m32c_push_rounding (int n)
+{
+ if (TARGET_R8C || TARGET_M16C)
+ return n;
+ return (n + 1) & ~1;
+}
+
+/* Passing Arguments in Registers */
+
+/* Implements FUNCTION_ARG. Arguments are passed partly in registers,
+ partly on stack. If our function returns a struct, a pointer to a
+ buffer for it is at the top of the stack (last thing pushed). The
+ first few real arguments may be in registers as follows:
+
+ R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
+ arg2 in r2 if it's HI (else pushed on stack)
+ rest on stack
+ M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
+ rest on stack
+
+ Structs are not passed in registers, even if they fit. Only
+ integer and pointer types are passed in registers.
+
+ Note that when arg1 doesn't fit in r1, arg2 may still be passed in
+ r2 if it fits. */
+rtx
+m32c_function_arg (CUMULATIVE_ARGS * ca,
+ enum machine_mode mode, tree type, int named)
+{
+ /* Can return a reg, parallel, or 0 for stack */
+ rtx rv = NULL_RTX;
+#if DEBUG0
+ fprintf (stderr, "func_arg %d (%s, %d)\n",
+ ca->parm_num, mode_name[mode], named);
+ debug_tree (type);
+#endif
+
+ if (mode == VOIDmode)
+ return GEN_INT (0);
+
+ if (ca->force_mem || !named)
+ {
+#if DEBUG0
+ fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
+ named);
+#endif
+ return NULL_RTX;
+ }
+
+ if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
+ return NULL_RTX;
+
+ switch (ca->parm_num)
+ {
+ case 1:
+ if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
+ rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
+ break;
+
+ case 2:
+ if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
+ rv = gen_rtx_REG (mode, R2_REGNO);
+ break;
+ }
+
+#if DEBUG0
+ debug_rtx (rv);
+#endif
+ return rv;
+}
+
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
+static bool
+m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type ATTRIBUTE_UNUSED,
+ bool named ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+/* Implements INIT_CUMULATIVE_ARGS. */
+void
+m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
+ tree fntype ATTRIBUTE_UNUSED,
+ rtx libname ATTRIBUTE_UNUSED,
+ tree fndecl ATTRIBUTE_UNUSED,
+ int n_named_args ATTRIBUTE_UNUSED)
+{
+ ca->force_mem = 0;
+ ca->parm_num = 1;
+}
+
+/* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
+ returning structures, so we always reset that. Otherwise, we only
+ need to know the sequence number of the argument to know what to do
+ with it. */
+void
+m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type ATTRIBUTE_UNUSED,
+ int named ATTRIBUTE_UNUSED)
+{
+ if (ca->force_mem)
+ ca->force_mem = 0;
+ ca->parm_num++;
+}
+
+/* Implements FUNCTION_ARG_REGNO_P. */
+int
+m32c_function_arg_regno_p (int r)
+{
+ if (TARGET_A24)
+ return (r == R0_REGNO);
+ return (r == R1_REGNO || r == R2_REGNO);
+}
+
+/* How Scalar Function Values Are Returned */
+
+/* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
+ combination of registers starting there (r2r0 for longs, r3r1r2r0
+ for long long, r3r2r1r0 for doubles), except that that ABI
+ currently doesn't work because it ends up using all available
+ general registers and gcc often can't compile it. So, instead, we
+ return anything bigger than 16 bits in "mem0" (effectively, a
+ memory location). */
+rtx
+m32c_libcall_value (enum machine_mode mode)
+{
+ /* return reg or parallel */
+#if 0
+ /* FIXME: GCC has difficulty returning large values in registers,
+ because that ties up most of the general registers and gives the
+ register allocator little to work with. Until we can resolve
+ this, large values are returned in memory. */
+ if (mode == DFmode)
+ {
+ rtx rv;
+
+ rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
+ XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (HImode,
+ R0_REGNO),
+ GEN_INT (0));
+ XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (HImode,
+ R1_REGNO),
+ GEN_INT (2));
+ XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (HImode,
+ R2_REGNO),
+ GEN_INT (4));
+ XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (HImode,
+ R3_REGNO),
+ GEN_INT (6));
+ return rv;
+ }
+
+ if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
+ {
+ rtx rv;
+
+ rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
+ XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (mode,
+ R0_REGNO),
+ GEN_INT (0));
+ return rv;
+ }
+#endif
+
+ if (GET_MODE_SIZE (mode) > 2)
+ return gen_rtx_REG (mode, MEM0_REGNO);
+ return gen_rtx_REG (mode, R0_REGNO);
+}
+
+/* Implements FUNCTION_VALUE. Functions and libcalls have the same
+ conventions. */
+rtx
+m32c_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
+{
+ /* return reg or parallel */
+ enum machine_mode mode = TYPE_MODE (valtype);
+ return m32c_libcall_value (mode);
+}
+
+/* How Large Values Are Returned */
+
+/* We return structures by pushing the address on the stack, even if
+ we use registers for the first few "real" arguments. */
+#undef TARGET_STRUCT_VALUE_RTX
+#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
+static rtx
+m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
+ int incoming ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+/* Function Entry and Exit */
+
+/* Implements EPILOGUE_USES. Interrupts restore all registers. */
+int
+m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
+{
+ if (cfun->machine->is_interrupt)
+ return 1;
+ return 0;
+}
+
+/* Implementing the Varargs Macros */
+
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
+static bool
+m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+/* Trampolines for Nested Functions */
+
+/*
+ m16c:
+ 1 0000 75C43412 mov.w #0x1234,a0
+ 2 0004 FC000000 jmp.a label
+
+ m32c:
+ 1 0000 BC563412 mov.l:s #0x123456,a0
+ 2 0004 CC000000 jmp.a label
+*/
+
+/* Implements TRAMPOLINE_SIZE. */
+int
+m32c_trampoline_size (void)
+{
+ /* Allocate extra space so we can avoid the messy shifts when we
+ initialize the trampoline; we just write past the end of the
+ opcode. */
+ return TARGET_A16 ? 8 : 10;
+}
+
+/* Implements TRAMPOLINE_ALIGNMENT. */
+int
+m32c_trampoline_alignment (void)
+{
+ return 2;
+}
+
+/* Implements INITIALIZE_TRAMPOLINE. */
+void
+m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
+{
+#define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
+ if (TARGET_A16)
+ {
+ /* Note: we subtract a "word" because the moves want signed
+ constants, not unsigned constants. */
+ emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
+ emit_move_insn (A0 (HImode, 2), chainval);
+ emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
+ /* We use 16 bit addresses here, but store the zero to turn it
+ into a 24 bit offset. */
+ emit_move_insn (A0 (HImode, 5), function);
+ emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
+ }
+ else
+ {
+ /* Note that the PSI moves actually write 4 bytes. Make sure we
+ write stuff out in the right order, and leave room for the
+ extra byte at the end. */
+ emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
+ emit_move_insn (A0 (PSImode, 1), chainval);
+ emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
+ emit_move_insn (A0 (PSImode, 5), function);
+ }
+#undef A0
+}
+
+/* Addressing Modes */
+
+/* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
+ wide range of non-orthogonal addressing modes, including the
+ ability to double-indirect on *some* of them. Not all insns
+ support all modes, either, but we rely on predicates and
+ constraints to deal with that. */
+int
+m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
+{
+ int mode_adjust;
+ if (CONSTANT_P (x))
+ return 1;
+
+ /* Wide references to memory will be split after reload, so we must
+ ensure that all parts of such splits remain legitimate
+ addresses. */
+ mode_adjust = GET_MODE_SIZE (mode) - 1;
+
+ /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
+ if (GET_CODE (x) == PRE_DEC
+ || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
+ {
+ return (GET_CODE (XEXP (x, 0)) == REG
+ && REGNO (XEXP (x, 0)) == SP_REGNO);
+ }
+
+#if 0
+ /* This is the double indirection detection, but it currently
+ doesn't work as cleanly as this code implies, so until we've had
+ a chance to debug it, leave it disabled. */
+ if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
+ {
+#if DEBUG_DOUBLE
+ fprintf (stderr, "double indirect\n");
+#endif
+ x = XEXP (x, 0);
+ }
+#endif
+
+ encode_pattern (x);
+ if (RTX_IS ("r"))
+ {
+ /* Most indexable registers can be used without displacements,
+ although some of them will be emitted with an explicit zero
+ to please the assembler. */
+ switch (REGNO (patternr[0]))
+ {
+ case A0_REGNO:
+ case A1_REGNO:
+ case SB_REGNO:
+ case FB_REGNO:
+ case SP_REGNO:
+ return 1;
+
+ default:
+ if (IS_PSEUDO (patternr[0], strict))
+ return 1;
+ return 0;
+ }
+ }
+ if (RTX_IS ("+ri"))
+ {
+ /* This is more interesting, because different base registers
+ allow for different displacements - both range and signedness
+ - and it differs from chip series to chip series too. */
+ int rn = REGNO (patternr[1]);
+ HOST_WIDE_INT offs = INTVAL (patternr[2]);
+ switch (rn)
+ {
+ case A0_REGNO:
+ case A1_REGNO:
+ case SB_REGNO:
+ /* The syntax only allows positive offsets, but when the
+ offsets span the entire memory range, we can simulate
+ negative offsets by wrapping. */
+ if (TARGET_A16)
+ return (offs >= -65536 && offs <= 65535 - mode_adjust);
+ if (rn == SB_REGNO)
+ return (offs >= 0 && offs <= 65535 - mode_adjust);
+ /* A0 or A1 */
+ return (offs >= -16777216 && offs <= 16777215);
+
+ case FB_REGNO:
+ if (TARGET_A16)
+ return (offs >= -128 && offs <= 127 - mode_adjust);
+ return (offs >= -65536 && offs <= 65535 - mode_adjust);
+
+ case SP_REGNO:
+ return (offs >= -128 && offs <= 127 - mode_adjust);
+
+ default:
+ if (IS_PSEUDO (patternr[1], strict))
+ return 1;
+ return 0;
+ }
+ }
+ if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
+ {
+ rtx reg = patternr[1];
+
+ /* We don't know where the symbol is, so only allow base
+ registers which support displacements spanning the whole
+ address range. */
+ switch (REGNO (reg))
+ {
+ case A0_REGNO:
+ case A1_REGNO:
+ /* $sb needs a secondary reload, but since it's involved in
+ memory address reloads too, we don't deal with it very
+ well. */
+ /* case SB_REGNO: */
+ return 1;
+ default:
+ if (IS_PSEUDO (reg, strict))
+ return 1;
+ return 0;
+ }
+ }
+ return 0;
+}
+
+/* Implements REG_OK_FOR_BASE_P. */
+int
+m32c_reg_ok_for_base_p (rtx x, int strict)
+{
+ if (GET_CODE (x) != REG)
+ return 0;
+ switch (REGNO (x))
+ {
+ case A0_REGNO:
+ case A1_REGNO:
+ case SB_REGNO:
+ case FB_REGNO:
+ case SP_REGNO:
+ return 1;
+ default:
+ if (IS_PSEUDO (x, strict))
+ return 1;
+ return 0;
+ }
+}
+
+/* Implements LEGITIMIZE_ADDRESS. The only address we really have to
+ worry about is frame base offsets, as $fb has a limited
+ displacement range. We deal with this by attempting to reload $fb
+ itself into an address register; that seems to result in the best
+ code. */
+int
+m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
+ rtx oldx ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+#if DEBUG0
+ fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
+ debug_rtx (*x);
+ fprintf (stderr, "\n");
+#endif
+
+ if (GET_CODE (*x) == PLUS
+ && GET_CODE (XEXP (*x, 0)) == REG
+ && REGNO (XEXP (*x, 0)) == FB_REGNO
+ && GET_CODE (XEXP (*x, 1)) == CONST_INT
+ && (INTVAL (XEXP (*x, 1)) < -128
+ || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
+ {
+ /* reload FB to A_REGS */
+ rtx foo;
+ rtx temp = gen_reg_rtx (Pmode);
+ *x = copy_rtx (*x);
+ foo = emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
+ XEXP (*x, 0) = temp;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
+int
+m32c_legitimize_reload_address (rtx * x,
+ enum machine_mode mode,
+ int opnum,
+ int type, int ind_levels ATTRIBUTE_UNUSED)
+{
+#if DEBUG0
+ fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
+ mode_name[mode]);
+ debug_rtx (*x);
+#endif
+
+ /* At one point, this function tried to get $fb copied to an address
+ register, which in theory would maximize sharing, but gcc was
+ *also* still trying to reload the whole address, and we'd run out
+ of address registers. So we let gcc do the naive (but safe)
+ reload instead, when the above function doesn't handle it for
+ us. */
+
+ return 0;
+}
+
+/* Used in GO_IF_MODE_DEPENDENT_ADDRESS. */
+int
+m32c_mode_dependent_address (rtx addr)
+{
+ if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == PRE_DEC)
+ return 1;
+ return 0;
+}
+
+/* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
+ so we can allow anything. */
+int
+m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+
+/* Condition Code Status */
+
+#undef TARGET_FIXED_CONDITION_CODE_REGS
+#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
+static bool
+m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
+{
+ *p1 = FLG_REGNO;
+ *p2 = INVALID_REGNUM;
+ return true;
+}
+
+/* Describing Relative Costs of Operations */
+
+/* Implements REGISTER_MOVE_COST. We make impossible moves
+ prohibitively expensive, like trying to put QIs in r2/r3 (there are
+ no opcodes to do that). We also discourage use of mem* registers
+ since they're really memory. */
+int
+m32c_register_move_cost (enum machine_mode mode, int from, int to)
+{
+ int cost = COSTS_N_INSNS (3);
+ int cc = class_contents[from][0] | class_contents[to][0];
+ /* FIXME: pick real values, but not 2 for now. */
+ if (mode == QImode && (cc & class_contents[R23_REGS][0]))
+ {
+ if (!(cc & ~class_contents[R23_REGS][0]))
+ cost = COSTS_N_INSNS (1000);
+ else
+ cost = COSTS_N_INSNS (80);
+ }
+
+ if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
+ cost = COSTS_N_INSNS (1000);
+
+ if (classes_intersect (from, CR_REGS))
+ cost += COSTS_N_INSNS (5);
+
+ if (classes_intersect (to, CR_REGS))
+ cost += COSTS_N_INSNS (5);
+
+ if (from == MEM_REGS || to == MEM_REGS)
+ cost += COSTS_N_INSNS (50);
+ else if (classes_intersect (from, MEM_REGS)
+ || classes_intersect (to, MEM_REGS))
+ cost += COSTS_N_INSNS (10);
+
+#if DEBUG0
+ fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
+ mode_name[mode], class_names[from], class_names[to], cost);
+#endif
+ return cost;
+}
+
+/* Implements MEMORY_MOVE_COST. */
+int
+m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+ int reg_class ATTRIBUTE_UNUSED,
+ int in ATTRIBUTE_UNUSED)
+{
+ /* FIXME: pick real values. */
+ return COSTS_N_INSNS (10);
+}
+
+/* Defining the Output Assembler Language */
+
+/* The Overall Framework of an Assembler File */
+
+#undef TARGET_HAVE_NAMED_SECTIONS
+#define TARGET_HAVE_NAMED_SECTIONS true
+
+/* Output of Data */
+
+/* We may have 24 bit sizes, which is the native address size.
+ Currently unused, but provided for completeness. */
+#undef TARGET_ASM_INTEGER
+#define TARGET_ASM_INTEGER m32c_asm_integer
+static bool
+m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
+{
+ switch (size)
+ {
+ case 3:
+ fprintf (asm_out_file, "\t.3byte\t");
+ output_addr_const (asm_out_file, x);
+ fputc ('\n', asm_out_file);
+ return true;
+ }
+ return default_assemble_integer (x, size, aligned_p);
+}
+
+/* Output of Assembler Instructions */
+
+/* We use a lookup table because the addressing modes are non-orthagonal. */
+
+static struct
+{
+ char code;
+ char const *pattern;
+ char const *format;
+}
+const conversions[] = {
+ { 0, "r", "0" },
+
+ { 0, "mr", "z[1]" },
+ { 0, "m+ri", "3[2]" },
+ { 0, "m+rs", "3[2]" },
+ { 0, "m+r+si", "4+5[2]" },
+ { 0, "ms", "1" },
+ { 0, "mi", "1" },
+ { 0, "m+si", "2+3" },
+
+ { 0, "mmr", "[z[2]]" },
+ { 0, "mm+ri", "[4[3]]" },
+ { 0, "mm+rs", "[4[3]]" },
+ { 0, "mm+r+si", "[5+6[3]]" },
+ { 0, "mms", "[[2]]" },
+ { 0, "mmi", "[[2]]" },
+ { 0, "mm+si", "[4[3]]" },
+
+ { 0, "i", "#0" },
+ { 0, "s", "#0" },
+ { 0, "+si", "#1+2" },
+ { 0, "l", "#0" },
+
+ { 'l', "l", "0" },
+ { 'd', "i", "0" },
+ { 'd', "s", "0" },
+ { 'd', "+si", "1+2" },
+ { 'D', "i", "0" },
+ { 'D', "s", "0" },
+ { 'D', "+si", "1+2" },
+ { 'x', "i", "#0" },
+ { 'X', "i", "#0" },
+ { 'm', "i", "#0" },
+ { 'b', "i", "#0" },
+ { 'p', "i", "0" },
+
+ { 0, 0, 0 }
+};
+
+/* This is in order according to the bitfield that pushm/popm use. */
+static char const *pushm_regs[] = {
+ "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
+};
+
+/* Implements PRINT_OPERAND. */
+void
+m32c_print_operand (FILE * file, rtx x, int code)
+{
+ int i, j, b;
+ const char *comma;
+ HOST_WIDE_INT ival;
+ int unsigned_const = 0;
+
+ /* Multiplies; constants are converted to sign-extended format but
+ we need unsigned, so 'u' and 'U' tell us what size unsigned we
+ need. */
+ if (code == 'u')
+ {
+ unsigned_const = 2;
+ code = 0;
+ }
+ if (code == 'U')
+ {
+ unsigned_const = 1;
+ code = 0;
+ }
+ /* This one is only for debugging; you can put it in a pattern to
+ force this error. */
+ if (code == '!')
+ {
+ fprintf (stderr, "dj: unreviewed pattern:");
+ if (current_output_insn)
+ debug_rtx (current_output_insn);
+ gcc_unreachable ();
+ }
+ /* PSImode operations are either .w or .l depending on the target. */
+ if (code == '&')
+ {
+ if (TARGET_A16)
+ fprintf (file, "w");
+ else
+ fprintf (file, "l");
+ return;
+ }
+ /* Inverted conditionals. */
+ if (code == 'C')
+ {
+ switch (GET_CODE (x))
+ {
+ case LE:
+ fputs ("gt", file);
+ break;
+ case LEU:
+ fputs ("gtu", file);
+ break;
+ case LT:
+ fputs ("ge", file);
+ break;
+ case LTU:
+ fputs ("geu", file);
+ break;
+ case GT:
+ fputs ("le", file);
+ break;
+ case GTU:
+ fputs ("leu", file);
+ break;
+ case GE:
+ fputs ("lt", file);
+ break;
+ case GEU:
+ fputs ("ltu", file);
+ break;
+ case NE:
+ fputs ("eq", file);
+ break;
+ case EQ:
+ fputs ("ne", file);
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ return;
+ }
+ /* Regular conditionals. */
+ if (code == 'c')
+ {
+ switch (GET_CODE (x))
+ {
+ case LE:
+ fputs ("le", file);
+ break;
+ case LEU:
+ fputs ("leu", file);
+ break;
+ case LT:
+ fputs ("lt", file);
+ break;
+ case LTU:
+ fputs ("ltu", file);
+ break;
+ case GT:
+ fputs ("gt", file);
+ break;
+ case GTU:
+ fputs ("gtu", file);
+ break;
+ case GE:
+ fputs ("ge", file);
+ break;
+ case GEU:
+ fputs ("geu", file);
+ break;
+ case NE:
+ fputs ("ne", file);
+ break;
+ case EQ:
+ fputs ("eq", file);
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ return;
+ }
+ /* Used in negsi2 to do HImode ops on the two parts of an SImode
+ operand. */
+ if (code == 'h' && GET_MODE (x) == SImode)
+ {
+ x = m32c_subreg (HImode, x, SImode, 0);
+ code = 0;
+ }
+ if (code == 'H' && GET_MODE (x) == SImode)
+ {
+ x = m32c_subreg (HImode, x, SImode, 2);
+ code = 0;
+ }
+ /* 'x' and 'X' need to be ignored for non-immediates. */
+ if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
+ code = 0;
+
+ encode_pattern (x);
+ for (i = 0; conversions[i].pattern; i++)
+ if (conversions[i].code == code
+ && streq (conversions[i].pattern, pattern))
+ {
+ for (j = 0; conversions[i].format[j]; j++)
+ /* backslash quotes the next character in the output pattern. */
+ if (conversions[i].format[j] == '\\')
+ {
+ fputc (conversions[i].format[j + 1], file);
+ j++;
+ }
+ /* Digits in the output pattern indicate that the
+ corresponding RTX is to be output at that point. */
+ else if (ISDIGIT (conversions[i].format[j]))
+ {
+ rtx r = patternr[conversions[i].format[j] - '0'];
+ switch (GET_CODE (r))
+ {
+ case REG:
+ fprintf (file, "%s",
+ reg_name_with_mode (REGNO (r), GET_MODE (r)));
+ break;
+ case CONST_INT:
+ switch (code)
+ {
+ case 'b':
+ /* Bit position. */
+ fprintf (file, "%d", (int) exact_log2 (INTVAL (r)));
+ break;
+ case 'x':
+ /* Unsigned byte. */
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX,
+ INTVAL (r) & 0xff);
+ break;
+ case 'X':
+ /* Unsigned word. */
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX,
+ INTVAL (r) & 0xffff);
+ break;
+ case 'p':
+ /* pushm and popm encode a register set into a single byte. */
+ comma = "";
+ for (b = 7; b >= 0; b--)
+ if (INTVAL (r) & (1 << b))
+ {
+ fprintf (file, "%s%s", comma, pushm_regs[b]);
+ comma = ",";
+ }
+ break;
+ case 'm':
+ /* "Minus". Output -X */
+ ival = (-INTVAL (r) & 0xffff);
+ if (ival & 0x8000)
+ ival = ival - 0x10000;
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
+ break;
+ default:
+ ival = INTVAL (r);
+ if (conversions[i].format[j + 1] == '[' && ival < 0)
+ {
+ /* We can simulate negative displacements by
+ taking advantage of address space
+ wrapping when the offset can span the
+ entire address range. */
+ rtx base =
+ patternr[conversions[i].format[j + 2] - '0'];
+ if (GET_CODE (base) == REG)
+ switch (REGNO (base))
+ {
+ case A0_REGNO:
+ case A1_REGNO:
+ if (TARGET_A24)
+ ival = 0x1000000 + ival;
+ else
+ ival = 0x10000 + ival;
+ break;
+ case SB_REGNO:
+ if (TARGET_A16)
+ ival = 0x10000 + ival;
+ break;
+ }
+ }
+ else if (code == 'd' && ival < 0 && j == 0)
+ /* The "mova" opcode is used to do addition by
+ computing displacements, but again, we need
+ displacements to be unsigned *if* they're
+ the only component of the displacement
+ (i.e. no "symbol-4" type displacement). */
+ ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
+
+ if (conversions[i].format[j] == '0')
+ {
+ /* More conversions to unsigned. */
+ if (unsigned_const == 2)
+ ival &= 0xffff;
+ if (unsigned_const == 1)
+ ival &= 0xff;
+ }
+ if (streq (conversions[i].pattern, "mi")
+ || streq (conversions[i].pattern, "mmi"))
+ {
+ /* Integers used as addresses are unsigned. */
+ ival &= (TARGET_A24 ? 0xffffff : 0xffff);
+ }
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
+ break;
+ }
+ break;
+ case CONST_DOUBLE:
+ /* We don't have const_double constants. If it
+ happens, make it obvious. */
+ fprintf (file, "[const_double 0x%lx]",
+ (unsigned long) CONST_DOUBLE_HIGH (r));
+ break;
+ case SYMBOL_REF:
+ assemble_name (file, XSTR (r, 0));
+ break;
+ case LABEL_REF:
+ output_asm_label (r);
+ break;
+ default:
+ fprintf (stderr, "don't know how to print this operand:");
+ debug_rtx (r);
+ gcc_unreachable ();
+ }
+ }
+ else
+ {
+ if (conversions[i].format[j] == 'z')
+ {
+ /* Some addressing modes *must* have a displacement,
+ so insert a zero here if needed. */
+ int k;
+ for (k = j + 1; conversions[i].format[k]; k++)
+ if (ISDIGIT (conversions[i].format[k]))
+ {
+ rtx reg = patternr[conversions[i].format[k] - '0'];
+ if (GET_CODE (reg) == REG
+ && (REGNO (reg) == SB_REGNO
+ || REGNO (reg) == FB_REGNO
+ || REGNO (reg) == SP_REGNO))
+ fputc ('0', file);
+ }
+ continue;
+ }
+ /* Signed displacements off symbols need to have signs
+ blended cleanly. */
+ if (conversions[i].format[j] == '+'
+ && (!code || code == 'I')
+ && ISDIGIT (conversions[i].format[j + 1])
+ && GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
+ == CONST_INT
+ && INTVAL (patternr[conversions[i].format[j + 1] - '0']) <
+ 0)
+ continue;
+ fputc (conversions[i].format[j], file);
+ }
+ break;
+ }
+ if (!conversions[i].pattern)
+ {
+ fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
+ pattern);
+ debug_rtx (x);
+ fprintf (file, "[%c.%s]", code ? code : '-', pattern);
+ }
+
+ return;
+}
+
+/* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
+ above for descriptions of what these do. */
+int
+m32c_print_operand_punct_valid_p (int c)
+{
+ if (c == '&' || c == '!')
+ return 1;
+ return 0;
+}
+
+/* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
+void
+m32c_print_operand_address (FILE * stream, rtx address)
+{
+ gcc_assert (GET_CODE (address) == MEM);
+ m32c_print_operand (stream, XEXP (address, 0), 0);
+}
+
+/* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
+ differently than general registers. */
+void
+m32c_output_reg_push (FILE * s, int regno)
+{
+ if (regno == FLG_REGNO)
+ fprintf (s, "\tpushc\tflg\n");
+ else
+ fprintf (s, "\tpush.%c\t%s",
+ " bwll"[reg_push_size (regno)], reg_names[regno]);
+}
+
+/* Likewise for ASM_OUTPUT_REG_POP. */
+void
+m32c_output_reg_pop (FILE * s, int regno)
+{
+ if (regno == FLG_REGNO)
+ fprintf (s, "\tpopc\tflg\n");
+ else
+ fprintf (s, "\tpop.%c\t%s",
+ " bwll"[reg_push_size (regno)], reg_names[regno]);
+}
+
+/* Defining target-specific uses of `__attribute__' */
+
+/* Used to simplify the logic below. Find the attributes wherever
+ they may be. */
+#define M32C_ATTRIBUTES(decl) \
+ (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
+ : DECL_ATTRIBUTES (decl) \
+ ? (DECL_ATTRIBUTES (decl)) \
+ : TYPE_ATTRIBUTES (TREE_TYPE (decl))
+
+/* Returns TRUE if the given tree has the "interrupt" attribute. */
+static int
+interrupt_p (tree node ATTRIBUTE_UNUSED)
+{
+ tree list = M32C_ATTRIBUTES (node);
+ while (list)
+ {
+ if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
+ return 1;
+ list = TREE_CHAIN (list);
+ }
+ return 0;
+}
+
+static tree
+interrupt_handler (tree * node ATTRIBUTE_UNUSED,
+ tree name ATTRIBUTE_UNUSED,
+ tree args ATTRIBUTE_UNUSED,
+ int flags ATTRIBUTE_UNUSED,
+ bool * no_add_attrs ATTRIBUTE_UNUSED)
+{
+ return NULL_TREE;
+}
+
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
+static const struct attribute_spec m32c_attribute_table[] = {
+ {"interrupt", 0, 0, false, false, false, interrupt_handler},
+ {0, 0, 0, 0, 0, 0, 0}
+};
+
+#undef TARGET_COMP_TYPE_ATTRIBUTES
+#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
+static int
+m32c_comp_type_attributes (tree type1 ATTRIBUTE_UNUSED,
+ tree type2 ATTRIBUTE_UNUSED)
+{
+ /* 0=incompatible 1=compatible 2=warning */
+ return 1;
+}
+
+#undef TARGET_INSERT_ATTRIBUTES
+#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
+static void
+m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
+ tree * attr_ptr ATTRIBUTE_UNUSED)
+{
+ /* Nothing to do here. */
+}
+
+/* Predicates */
+
+/* Returns TRUE if we support a move between the first two operands.
+ At the moment, we just want to discourage mem to mem moves until
+ after reload, because reload has a hard time with our limited
+ number of address registers, and we can get into a situation where
+ we need three of them when we only have two. */
+bool
+m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+
+ if (TARGET_A24)
+ return true;
+
+#define DEBUG_MOV_OK 0
+#if DEBUG_MOV_OK
+ fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
+ debug_rtx (op0);
+ debug_rtx (op1);
+#endif
+
+ if (GET_CODE (op0) == SUBREG)
+ op0 = XEXP (op0, 0);
+ if (GET_CODE (op1) == SUBREG)
+ op1 = XEXP (op1, 0);
+
+ if (GET_CODE (op0) == MEM
+ && GET_CODE (op1) == MEM
+ && ! reload_completed)
+ {
+#if DEBUG_MOV_OK
+ fprintf (stderr, " - no, mem to mem\n");
+#endif
+ return false;
+ }
+
+#if DEBUG_MOV_OK
+ fprintf (stderr, " - ok\n");
+#endif
+ return true;
+}
+
+/* Expanders */
+
+/* Subregs are non-orthogonal for us, because our registers are all
+ different sizes. */
+static rtx
+m32c_subreg (enum machine_mode outer,
+ rtx x, enum machine_mode inner, int byte)
+{
+ int r, nr = -1;
+
+ /* Converting MEMs to different types that are the same size, we
+ just rewrite them. */
+ if (GET_CODE (x) == SUBREG
+ && SUBREG_BYTE (x) == 0
+ && GET_CODE (SUBREG_REG (x)) == MEM
+ && (GET_MODE_SIZE (GET_MODE (x))
+ == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
+ {
+ rtx oldx = x;
+ x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
+ MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
+ }
+
+ /* Push/pop get done as smaller push/pops. */
+ if (GET_CODE (x) == MEM
+ && (GET_CODE (XEXP (x, 0)) == PRE_DEC
+ || GET_CODE (XEXP (x, 0)) == POST_INC))
+ return gen_rtx_MEM (outer, XEXP (x, 0));
+ if (GET_CODE (x) == SUBREG
+ && GET_CODE (XEXP (x, 0)) == MEM
+ && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
+ || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
+ return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
+
+ if (GET_CODE (x) != REG)
+ return simplify_gen_subreg (outer, x, inner, byte);
+
+ r = REGNO (x);
+ if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
+ return simplify_gen_subreg (outer, x, inner, byte);
+
+ if (IS_MEM_REGNO (r))
+ return simplify_gen_subreg (outer, x, inner, byte);
+
+ /* This is where the complexities of our register layout are
+ described. */
+ if (byte == 0)
+ nr = r;
+ else if (outer == HImode)
+ {
+ if (r == R0_REGNO && byte == 2)
+ nr = R2_REGNO;
+ else if (r == R0_REGNO && byte == 4)
+ nr = R1_REGNO;
+ else if (r == R0_REGNO && byte == 6)
+ nr = R3_REGNO;
+ else if (r == R1_REGNO && byte == 2)
+ nr = R3_REGNO;
+ else if (r == A0_REGNO && byte == 2)
+ nr = A1_REGNO;
+ }
+ else if (outer == SImode)
+ {
+ if (r == R0_REGNO && byte == 0)
+ nr = R0_REGNO;
+ else if (r == R0_REGNO && byte == 4)
+ nr = R1_REGNO;
+ }
+ if (nr == -1)
+ {
+ fprintf (stderr, "m32c_subreg %s %s %d\n",
+ mode_name[outer], mode_name[inner], byte);
+ debug_rtx (x);
+ gcc_unreachable ();
+ }
+ return gen_rtx_REG (outer, nr);
+}
+
+/* Used to emit move instructions. We split some moves,
+ and avoid mem-mem moves. */
+int
+m32c_prepare_move (rtx * operands, enum machine_mode mode)
+{
+ if (TARGET_A16 && mode == PSImode)
+ return m32c_split_move (operands, mode, 1);
+ if ((GET_CODE (operands[0]) == MEM)
+ && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
+ {
+ rtx pmv = XEXP (operands[0], 0);
+ rtx dest_reg = XEXP (pmv, 0);
+ rtx dest_mod = XEXP (pmv, 1);
+
+ emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
+ operands[0] = gen_rtx_MEM (mode, dest_reg);
+ }
+ if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
+ operands[1] = copy_to_mode_reg (mode, operands[1]);
+ return 0;
+}
+
+#define DEBUG_SPLIT 0
+
+/* Returns TRUE if the given PSImode move should be split. We split
+ for all r8c/m16c moves, since it doesn't support them, and for
+ POP.L as we can only *push* SImode. */
+int
+m32c_split_psi_p (rtx * operands)
+{
+#if DEBUG_SPLIT
+ fprintf (stderr, "\nm32c_split_psi_p\n");
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+#endif
+ if (TARGET_A16)
+ {
+#if DEBUG_SPLIT
+ fprintf (stderr, "yes, A16\n");
+#endif
+ return 1;
+ }
+ if (GET_CODE (operands[1]) == MEM
+ && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
+ {
+#if DEBUG_SPLIT
+ fprintf (stderr, "yes, pop.l\n");
+#endif
+ return 1;
+ }
+#if DEBUG_SPLIT
+ fprintf (stderr, "no, default\n");
+#endif
+ return 0;
+}
+
+/* Split the given move. SPLIT_ALL is 0 if splitting is optional
+ (define_expand), 1 if it is not optional (define_insn_and_split),
+ and 3 for define_split (alternate api). */
+int
+m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
+{
+ rtx s[4], d[4];
+ int parts, si, di, rev = 0;
+ int rv = 0, opi = 2;
+ enum machine_mode submode = HImode;
+ rtx *ops, local_ops[10];
+
+ /* define_split modifies the existing operands, but the other two
+ emit new insns. OPS is where we store the operand pairs, which
+ we emit later. */
+ if (split_all == 3)
+ ops = operands;
+ else
+ ops = local_ops;
+
+ /* Else HImode. */
+ if (mode == DImode)
+ submode = SImode;
+
+ /* Before splitting mem-mem moves, force one operand into a
+ register. */
+ if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
+ {
+#if DEBUG0
+ fprintf (stderr, "force_reg...\n");
+ debug_rtx (operands[1]);
+#endif
+ operands[1] = force_reg (mode, operands[1]);
+#if DEBUG0
+ debug_rtx (operands[1]);
+#endif
+ }
+
+ parts = 2;
+
+#if DEBUG_SPLIT
+ fprintf (stderr, "\nsplit_move %d all=%d\n", no_new_pseudos, split_all);
+ debug_rtx (operands[0]);
+ debug_rtx (operands[1]);
+#endif
+
+ /* We don't need to split these. */
+ if (TARGET_A24
+ && split_all != 3
+ && (mode == SImode || mode == PSImode)
+ && !(GET_CODE (operands[1]) == MEM
+ && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
+ return 0;
+
+ /* First, enumerate the subregs we'll be dealing with. */
+ for (si = 0; si < parts; si++)
+ {
+ d[si] =
+ m32c_subreg (submode, operands[0], mode,
+ si * GET_MODE_SIZE (submode));
+ s[si] =
+ m32c_subreg (submode, operands[1], mode,
+ si * GET_MODE_SIZE (submode));
+ }
+
+ /* Split pushes by emitting a sequence of smaller pushes. */
+ if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
+ {
+ for (si = parts - 1; si >= 0; si--)
+ {
+ ops[opi++] = gen_rtx_MEM (submode,
+ gen_rtx_PRE_DEC (Pmode,
+ gen_rtx_REG (Pmode,
+ SP_REGNO)));
+ ops[opi++] = s[si];
+ }
+
+ rv = 1;
+ }
+ /* Likewise for pops. */
+ else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
+ {
+ for (di = 0; di < parts; di++)
+ {
+ ops[opi++] = d[di];
+ ops[opi++] = gen_rtx_MEM (submode,
+ gen_rtx_POST_INC (Pmode,
+ gen_rtx_REG (Pmode,
+ SP_REGNO)));
+ }
+ rv = 1;
+ }
+ else if (split_all)
+ {
+ /* if d[di] == s[si] for any di < si, we'll early clobber. */
+ for (di = 0; di < parts - 1; di++)
+ for (si = di + 1; si < parts; si++)
+ if (reg_mentioned_p (d[di], s[si]))
+ rev = 1;
+
+ if (rev)
+ for (si = 0; si < parts; si++)
+ {
+ ops[opi++] = d[si];
+ ops[opi++] = s[si];
+ }
+ else
+ for (si = parts - 1; si >= 0; si--)
+ {
+ ops[opi++] = d[si];
+ ops[opi++] = s[si];
+ }
+ rv = 1;
+ }
+ /* Now emit any moves we may have accumulated. */
+ if (rv && split_all != 3)
+ {
+ int i;
+ for (i = 2; i < opi; i += 2)
+ emit_move_insn (ops[i], ops[i + 1]);
+ }
+ return rv;
+}
+
+/* The m32c only has one shift, but it takes a signed count. GCC
+ doesn't want this, so we fake it by negating any shift count when
+ we're pretending to shift the other way. */
+int
+m32c_prepare_shift (rtx * operands, int scale, int bits)
+{
+ rtx temp;
+ if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) <= (1 << (bits - 1))
+ && INTVAL (operands[2]) >= -(1 << (bits - 1)))
+ {
+ operands[2] = GEN_INT (scale * INTVAL (operands[2]));
+ return 0;
+ }
+ if (scale < 0)
+ {
+ temp = gen_reg_rtx (QImode);
+ if (GET_CODE (operands[2]) == CONST_INT)
+ temp = GEN_INT (-INTVAL (operands[2]));
+ else
+ emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
+ }
+ else
+ temp = operands[2];
+ operands[2] = temp;
+ return 0;
+}
+
+/* Pattern Output Functions */
+
+/* Returns TRUE if the current function is a leaf, and thus we can
+ determine which registers an interrupt function really needs to
+ save. The logic below is mostly about finding the insn sequence
+ that's the function, versus any sequence that might be open for the
+ current insn. */
+static int
+m32c_leaf_function_p (void)
+{
+ rtx saved_first, saved_last;
+ struct sequence_stack *seq;
+ int rv;
+
+ saved_first = cfun->emit->x_first_insn;
+ saved_last = cfun->emit->x_last_insn;
+ for (seq = cfun->emit->sequence_stack; seq && seq->next; seq = seq->next)
+ ;
+ if (seq)
+ {
+ cfun->emit->x_first_insn = seq->first;
+ cfun->emit->x_last_insn = seq->last;
+ }
+
+ rv = leaf_function_p ();
+
+ cfun->emit->x_first_insn = saved_first;
+ cfun->emit->x_last_insn = saved_last;
+ return rv;
+}
+
+/* Returns TRUE if the current function needs to use the ENTER/EXIT
+ opcodes. If the function doesn't need the frame base or stack
+ pointer, it can use the simpler RTS opcode. */
+static bool
+m32c_function_needs_enter (void)
+{
+ rtx insn;
+ struct sequence_stack *seq;
+ rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
+ rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
+
+ insn = get_insns ();
+ for (seq = cfun->emit->sequence_stack;
+ seq;
+ insn = seq->first, seq = seq->next);
+
+ while (insn)
+ {
+ if (reg_mentioned_p (sp, insn))
+ return true;
+ if (reg_mentioned_p (fb, insn))
+ return true;
+ insn = NEXT_INSN (insn);
+ }
+ return false;
+}
+
+/* Mark all the subexpressions of the PARALLEL rtx PAR as
+ frame-related. Return PAR.
+
+ dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
+ PARALLEL rtx other than the first if they do not have the
+ FRAME_RELATED flag set on them. So this function is handy for
+ marking up 'enter' instructions. */
+static rtx
+m32c_all_frame_related (rtx par)
+{
+ int len = XVECLEN (par, 0);
+ int i;
+
+ for (i = 0; i < len; i++)
+ F (XVECEXP (par, 0, i));
+
+ return par;
+}
+
+/* Emits the prologue. See the frame layout comment earlier in this
+ file. We can reserve up to 256 bytes with the ENTER opcode, beyond
+ that we manually update sp. */
+void
+m32c_emit_prologue (void)
+{
+ int frame_size, extra_frame_size = 0, reg_save_size;
+ int complex_prologue = 0;
+
+ cfun->machine->is_leaf = m32c_leaf_function_p ();
+ if (interrupt_p (cfun->decl))
+ {
+ cfun->machine->is_interrupt = 1;
+ complex_prologue = 1;
+ }
+
+ reg_save_size = m32c_pushm_popm (PP_justcount);
+
+ if (interrupt_p (cfun->decl))
+ emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
+
+ frame_size =
+ m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
+ if (frame_size == 0
+ && !cfun->machine->is_interrupt
+ && !m32c_function_needs_enter ())
+ cfun->machine->use_rts = 1;
+
+ if (frame_size > 254)
+ {
+ extra_frame_size = frame_size - 254;
+ frame_size = 254;
+ }
+ if (cfun->machine->use_rts == 0)
+ F (emit_insn (m32c_all_frame_related
+ (TARGET_A16
+ ? gen_prologue_enter_16 (GEN_INT (frame_size))
+ : gen_prologue_enter_24 (GEN_INT (frame_size)))));
+
+ if (extra_frame_size)
+ {
+ complex_prologue = 1;
+ if (TARGET_A16)
+ F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
+ gen_rtx_REG (HImode, SP_REGNO),
+ GEN_INT (-extra_frame_size))));
+ else
+ F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
+ gen_rtx_REG (PSImode, SP_REGNO),
+ GEN_INT (-extra_frame_size))));
+ }
+
+ complex_prologue += m32c_pushm_popm (PP_pushm);
+
+ /* This just emits a comment into the .s file for debugging. */
+ if (complex_prologue)
+ emit_insn (gen_prologue_end ());
+}
+
+/* Likewise, for the epilogue. The only exception is that, for
+ interrupts, we must manually unwind the frame as the REIT opcode
+ doesn't do that. */
+void
+m32c_emit_epilogue (void)
+{
+ /* This just emits a comment into the .s file for debugging. */
+ if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
+ emit_insn (gen_epilogue_start ());
+
+ m32c_pushm_popm (PP_popm);
+
+ if (cfun->machine->is_interrupt)
+ {
+ enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
+
+ emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
+ gen_rtx_REG (spmode, FP_REGNO));
+ emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
+ gen_rtx_REG (spmode, A0_REGNO));
+ if (TARGET_A16)
+ emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
+ else
+ emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
+ emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
+ emit_jump_insn (gen_epilogue_reit (GEN_INT (TARGET_A16 ? 4 : 6)));
+ }
+ else if (cfun->machine->use_rts)
+ emit_jump_insn (gen_epilogue_rts ());
+ else
+ emit_jump_insn (gen_epilogue_exitd (GEN_INT (TARGET_A16 ? 2 : 4)));
+ emit_barrier ();
+}
+
+void
+m32c_emit_eh_epilogue (rtx ret_addr)
+{
+ /* R0[R2] has the stack adjustment. R1[R3] has the address to
+ return to. We have to fudge the stack, pop everything, pop SP
+ (fudged), and return (fudged). This is actually easier to do in
+ assembler, so punt to libgcc. */
+ emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
+ /* emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
+ emit_barrier ();
+}
+
+/* The Global `targetm' Variable. */
+
+struct gcc_target targetm = TARGET_INITIALIZER;
+
+#include "gt-m32c.h"
--- /dev/null
+/* Target Definitions for R8C/M16C/M32C
+ Copyright (C) 2005
+ Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#ifndef GCC_M32C_H
+#define GCC_M32C_H
+
+/* Controlling the Compilation Driver, `gcc'. */
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
+
+/* There are four CPU series we support, but they basically break down
+ into two families - the R8C/M16C families, with 16 bit address
+ registers and one set of opcodes, and the M32CM/M32C group, with 24
+ bit address registers and a different set of opcodes. The
+ assembler doesn't care except for which opcode set is needed; the
+ big difference is in the memory maps, which we cover in
+ LIB_SPEC. */
+
+#undef ASM_SPEC
+#define ASM_SPEC "\
+%{mcpu=r8c:--m16c} \
+%{mcpu=m16c:--m16c} \
+%{mcpu=m32cm:--m32c} \
+%{mcpu=m32c:--m32c} "
+
+/* The default is R8C hardware. We support a simulator, which has its
+ own libgloss and link map, plus one default link map for each chip
+ family. Most of the logic here is making sure we do the right
+ thing when no CPU is specified, which defaults to R8C. */
+#undef LIB_SPEC
+#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
+%{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \
+ %{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \
+%{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \
+ %{mcpu=m32cm:-Tm32cm.ld} \
+ %{mcpu=m32c:-Tm32c.ld} \
+ %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \
+"
+
+/* Run-time Target Specification */
+
+/* Nothing unusual here. */
+#define TARGET_CPU_CPP_BUILTINS() \
+ { \
+ builtin_assert ("cpu=m32c"); \
+ builtin_assert ("machine=m32c"); \
+ builtin_define ("__m32c__=1"); \
+ if (TARGET_R8C) \
+ builtin_define ("__r8c_cpu__=1"); \
+ if (TARGET_M16C) \
+ builtin_define ("__m16c_cpu__=1"); \
+ if (TARGET_M32CM) \
+ builtin_define ("__m32cm_cpu__=1"); \
+ if (TARGET_M32C) \
+ builtin_define ("__m32c_cpu__=1"); \
+ }
+
+/* The pragma handlers need to know if we've started processing
+ functions yet, as the memregs pragma should only be given at the
+ beginning of the file. This variable starts off TRUE and later
+ becomes FALSE. */
+extern int ok_to_change_target_memregs;
+extern int target_memregs;
+
+/* TARGET_CPU is a multi-way option set in m32c.opt. While we could
+ use enums or defines for this, this and m32c.opt are the only
+ places that know (or care) what values are being used. */
+#define TARGET_R8C (target_cpu == 'r')
+#define TARGET_M16C (target_cpu == '6')
+#define TARGET_M32CM (target_cpu == 'm')
+#define TARGET_M32C (target_cpu == '3')
+
+/* Address register sizes. Warning: these are used all over the place
+ to select between the two CPU families in general. */
+#define TARGET_A16 (TARGET_R8C || TARGET_M16C)
+#define TARGET_A24 (TARGET_M32CM || TARGET_M32C)
+
+#define TARGET_VERSION fprintf (stderr, " (m32c)");
+
+#define OVERRIDE_OPTIONS m32c_override_options ();
+
+/* Defining data structures for per-function information */
+
+typedef struct machine_function GTY (())
+{
+ /* How much we adjust the stack when returning from an exception
+ handler. */
+ rtx eh_stack_adjust;
+
+ /* TRUE if the current function is an interrupt handler. */
+ int is_interrupt;
+
+ /* TRUE if the current function is a leaf function. Currently, this
+ only affects saving $a0 in interrupt functions. */
+ int is_leaf;
+
+ /* Bitmask that keeps track of which registers are used in an
+ interrupt function, so we know which ones need to be saved and
+ restored. */
+ int intr_pushm;
+ /* Likewise, one element for each memreg that needs to be saved. */
+ char intr_pushmem[16];
+
+ /* TRUE if the current function can use a simple RTS to return, instead
+ of the longer ENTER/EXIT pair. */
+ int use_rts;
+}
+machine_function;
+
+#define INIT_EXPANDERS m32c_init_expanders ()
+
+/* Storage Layout */
+
+#define BITS_BIG_ENDIAN 0
+#define BYTES_BIG_ENDIAN 0
+#define WORDS_BIG_ENDIAN 0
+
+/* We can do QI, HI, and SI operations pretty much equally well, but
+ GCC expects us to have a "native" format, so we pick the one that
+ matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16
+ is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
+ 24 bit pointers are stored in 32 bit words. */
+#define BITS_PER_UNIT 8
+#define UNITS_PER_WORD 2
+#define POINTER_SIZE (TARGET_A16 ? 16 : 32)
+#define POINTERS_EXTEND_UNSIGNED 1
+
+/* These match the alignment enforced by the two types of stack operations. */
+#define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
+#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
+
+/* We do this because we care more about space than about speed. For
+ the chips with 16 bit busses, we could set these to 16 if
+ desired. */
+#define FUNCTION_BOUNDARY 8
+#define BIGGEST_ALIGNMENT 8
+
+#define STRICT_ALIGNMENT 0
+#define SLOW_BYTE_ACCESS 1
+
+/* Layout of Source Language Data Types */
+
+#define INT_TYPE_SIZE 16
+#define SHORT_TYPE_SIZE 16
+#define LONG_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 64
+
+#define FLOAT_TYPE_SIZE 32
+#define DOUBLE_TYPE_SIZE 64
+#define LONG_DOUBLE_TYPE_SIZE 64
+
+#define DEFAULT_SIGNED_CHAR 1
+
+/* REGISTER USAGE */
+
+/* Register Basics */
+
+/* Register layout:
+
+ [r0h][r0l] $r0 (16 bits, or two 8 bit halves)
+ [--------] $r2 (16 bits)
+ [r1h][r1l] $r1 (16 bits, or two 8 bit halves)
+ [--------] $r3 (16 bits)
+ [---][--------] $a0 (might be 24 bits)
+ [---][--------] $a1 (might be 24 bits)
+ [---][--------] $sb (might be 24 bits)
+ [---][--------] $fb (might be 24 bits)
+ [---][--------] $sp (might be 24 bits)
+ [-------------] $pc (20 or 24 bits)
+ [---] $flg (CPU flags)
+ [---][--------] $argp (virtual)
+ [--------] $mem0 (all 16 bits)
+ . . .
+ [--------] $mem14
+*/
+
+#define FIRST_PSEUDO_REGISTER 20
+
+/* Note that these two tables are modified based on which CPU family
+ you select; see m32c_conditional_register_usage for details. */
+
+/* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
+#define FIXED_REGISTERS { 0, 0, 0, 0, \
+ 0, 0, 1, 0, \
+ 1, 1, 0, 1, \
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+#define CALL_USED_REGISTERS { 1, 1, 1, 1, \
+ 1, 1, 1, 0, \
+ 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1 }
+
+#define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
+
+/* The *_REGNO theme matches m32c.md and most register number
+ arguments; the PC_REGNUM is the odd one out. */
+#ifndef PC_REGNO
+#define PC_REGNO 9
+#endif
+#define PC_REGNUM PC_REGNO
+
+/* How Values Fit in Registers */
+
+#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
+#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
+#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
+#define AVOID_CCMODE_COPIES
+
+/* Register Classes */
+
+/* Most registers are special purpose in some form or another, so this
+ table is pretty big. Class names are used for constraints also;
+ for example the HL_REGS class (HL below) is "Rhl" in the md files.
+ See m32c_reg_class_from_constraint for the mapping. There's some
+ duplication so that we can better isolate the reason for using
+ constraints in the md files from the actual registers used; for
+ example we may want to exclude a1a0 from SI_REGS in the future,
+ without precluding their use as HImode registers. */
+
+/* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
+/* mmPAR */
+#define REG_CLASS_CONTENTS \
+{ { 0x00000000 }, /* NO */\
+ { 0x00000100 }, /* SP - sp */\
+ { 0x00000080 }, /* FB - fb */\
+ { 0x00000040 }, /* SB - sb */\
+ { 0x000001c0 }, /* CR - sb fb sp */\
+ { 0x00000001 }, /* R0 - r0 */\
+ { 0x00000004 }, /* R1 - r1 */\
+ { 0x00000002 }, /* R2 - r2 */\
+ { 0x00000008 }, /* R3 - r3 */\
+ { 0x00000003 }, /* R02 - r0r2 */\
+ { 0x00000005 }, /* HL - r0 r1 */\
+ { 0x00000005 }, /* QI - r0 r1 */\
+ { 0x0000000a }, /* R23 - r2 r3 */\
+ { 0x0000000f }, /* R03 - r0r2 r1r3 */\
+ { 0x0000000f }, /* DI - r0r2r1r3 + mems */\
+ { 0x00000030 }, /* A - a0 a1 */\
+ { 0x000000f0 }, /* AD - a0 a1 sb fp */\
+ { 0x000001f0 }, /* PS - a0 a1 sb fp sp */\
+ { 0x0000003f }, /* SI - r0r2 r1r3 a0a1 */\
+ { 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\
+ { 0x0000003f }, /* RA - r0..r3 a0 a1 */\
+ { 0x0000007f }, /* GENERAL */\
+ { 0x00000400 }, /* FLG */\
+ { 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\
+ { 0x000ff000 }, /* MEM */\
+ { 0x000ff003 }, /* R02_A_MEM */\
+ { 0x000ff005 }, /* A_HL_MEM */\
+ { 0x000ff00c }, /* R1_R3_A_MEM */\
+ { 0x000ff00f }, /* R03_MEM */\
+ { 0x000ff03f }, /* A_HI_MEM */\
+ { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
+ { 0x000ff1ff }, /* ALL */\
+}
+
+enum reg_class
+{
+ NO_REGS,
+ SP_REGS,
+ FB_REGS,
+ SB_REGS,
+ CR_REGS,
+ R0_REGS,
+ R1_REGS,
+ R2_REGS,
+ R3_REGS,
+ R02_REGS,
+ HL_REGS,
+ QI_REGS,
+ R23_REGS,
+ R03_REGS,
+ DI_REGS,
+ A_REGS,
+ AD_REGS,
+ PS_REGS,
+ SI_REGS,
+ HI_REGS,
+ RA_REGS,
+ GENERAL_REGS,
+ FLG_REGS,
+ HC_REGS,
+ MEM_REGS,
+ R02_A_MEM_REGS,
+ A_HL_MEM_REGS,
+ R1_R3_A_MEM_REGS,
+ R03_MEM_REGS,
+ A_HI_MEM_REGS,
+ A_AD_CR_MEM_SI_REGS,
+ ALL_REGS,
+ LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES LIM_REG_CLASSES
+
+#define REG_CLASS_NAMES {\
+"NO_REGS", \
+"SP_REGS", \
+"FB_REGS", \
+"SB_REGS", \
+"CR_REGS", \
+"R0_REGS", \
+"R1_REGS", \
+"R2_REGS", \
+"R3_REGS", \
+"R02_REGS", \
+"HL_REGS", \
+"QI_REGS", \
+"R23_REGS", \
+"R03_REGS", \
+"DI_REGS", \
+"A_REGS", \
+"AD_REGS", \
+"PS_REGS", \
+"SI_REGS", \
+"HI_REGS", \
+"RA_REGS", \
+"GENERAL_REGS", \
+"FLG_REGS", \
+"HC_REGS", \
+"MEM_REGS", \
+"R02_A_MEM_REGS", \
+"A_HL_MEM_REGS", \
+"R1_R3_A_MEM_REGS", \
+"R03_MEM_REGS", \
+"A_HI_MEM_REGS", \
+"A_AD_CR_MEM_SI_REGS", \
+"ALL_REGS", \
+}
+
+#define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
+
+/* We support simple displacements off address registers, nothing else. */
+#define BASE_REG_CLASS A_REGS
+#define INDEX_REG_CLASS NO_REGS
+
+/* We primarily use the new "long" constraint names, with the intial
+ letter classifying the constraint type and following letters
+ specifying which. The types are:
+
+ I - integer values
+ R - register classes
+ S - memory references (M was used)
+ A - addresses (currently unused)
+*/
+
+#define CONSTRAINT_LEN(CHAR,STR) \
+ ((CHAR) == 'I' ? 3 \
+ : (CHAR) == 'R' ? 3 \
+ : (CHAR) == 'S' ? 2 \
+ : (CHAR) == 'A' ? 2 \
+ : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
+#define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
+ m32c_reg_class_from_constraint (CHAR, STR)
+
+#define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
+#define REGNO_OK_FOR_INDEX_P(NUM) 0
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
+#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
+#define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS)
+
+#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X)
+
+#define SMALL_REGISTER_CLASSES 1
+
+#define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C)
+
+#define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
+
+#define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
+
+#define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
+ m32c_const_ok_for_constraint_p (VALUE, C, STR)
+#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
+#define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
+ m32c_extra_constraint_p (VALUE, C, STR)
+#define EXTRA_MEMORY_CONSTRAINT(C,STR) \
+ m32c_extra_memory_constraint (C, STR)
+#define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
+ m32c_extra_address_constraint (C, STR)
+
+/* STACK AND CALLING */
+
+/* Frame Layout */
+
+/* Standard push/pop stack, no surprises here. */
+
+#define STACK_GROWS_DOWNWARD 1
+#define STACK_PUSH_CODE PRE_DEC
+#define FRAME_GROWS_DOWNWARD 1
+
+#define STARTING_FRAME_OFFSET 0
+#define FIRST_PARM_OFFSET(F) 0
+
+#define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
+
+#define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
+#define INCOMING_FRAME_SP_OFFSET 3
+
+/* Exception Handling Support */
+
+#define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
+#define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
+
+/* Registers That Address the Stack Frame */
+
+#ifndef FP_REGNO
+#define FP_REGNO 7
+#endif
+#ifndef SP_REGNO
+#define SP_REGNO 8
+#endif
+#define AP_REGNO 11
+
+#define STACK_POINTER_REGNUM SP_REGNO
+#define FRAME_POINTER_REGNUM FP_REGNO
+#define ARG_POINTER_REGNUM AP_REGNO
+
+/* The static chain must be pointer-capable. */
+#define STATIC_CHAIN_REGNUM A0_REGNO
+
+#define DWARF_FRAME_REGISTERS 20
+#define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
+#define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
+
+/* Eliminating Frame Pointer and Arg Pointer */
+
+/* If the frame pointer isn't used, we detect it manually. But the
+ stack pointer doesn't have as flexible addressing as the frame
+ pointer, so we always assume we have it. */
+#define FRAME_POINTER_REQUIRED 1
+
+#define ELIMINABLE_REGS \
+ {{AP_REGNO, SP_REGNO}, \
+ {AP_REGNO, FB_REGNO}, \
+ {FB_REGNO, SP_REGNO}}
+
+#define CAN_ELIMINATE(FROM,TO) 1
+#define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
+ (VAR) = m32c_initial_elimination_offset(FROM,TO)
+
+/* Passing Function Arguments on the Stack */
+
+#define PUSH_ARGS 1
+#define PUSH_ROUNDING(N) m32c_push_rounding (N)
+#define RETURN_POPS_ARGS(D,T,S) 0
+#define CALL_POPS_ARGS(C) 0
+
+/* Passing Arguments in Registers */
+
+#define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \
+ m32c_function_arg (&(CA),MODE,TYPE,NAMED)
+
+typedef struct m32c_cumulative_args
+{
+ /* For address of return value buffer (structures are returned by
+ passing the address of a buffer as an invisible first argument.
+ This identifies it). If set, the current parameter will be put
+ on the stack, regardless of type. */
+ int force_mem;
+ /* First parm is 1, parm 0 is hidden pointer for returning
+ aggregates. */
+ int parm_num;
+} m32c_cumulative_args;
+
+#define CUMULATIVE_ARGS m32c_cumulative_args
+#define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
+ m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
+#define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \
+ m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED)
+#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
+#define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
+
+/* How Scalar Function Values Are Returned */
+
+#define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F)
+#define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE)
+
+#define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO)
+
+/* How Large Values Are Returned */
+
+#define DEFAULT_PCC_STRUCT_RETURN 1
+
+/* Function Entry and Exit */
+
+#define EXIT_IGNORE_STACK 0
+#define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
+#define EH_USES(REGNO) 0 /* FIXME */
+
+/* Generating Code for Profiling */
+
+#define FUNCTION_PROFILER(FILE,LABELNO)
+
+/* Implementing the Varargs Macros */
+
+/* Trampolines for Nested Functions */
+
+#define TRAMPOLINE_SIZE m32c_trampoline_size ()
+#define TRAMPOLINE_ALIGMNENT m32c_trampoline_alignment ()
+#define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc)
+
+/* Addressing Modes */
+
+#define HAVE_PRE_DECREMENT 1
+#define HAVE_POST_INCREMENT 1
+#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
+#define MAX_REGS_PER_ADDRESS 1
+
+/* This is passed to the macros below, so that they can be implemented
+ in m32c.c. */
+#ifdef REG_OK_STRICT
+#define REG_OK_STRICT_V 1
+#else
+#define REG_OK_STRICT_V 0
+#endif
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \
+ if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \
+ goto LABEL;
+
+#define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
+#define REG_OK_FOR_INDEX_P(X) 0
+
+/* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
+ if (m32c_legitimize_address(&(X),OLDX,MODE)) \
+ goto win;
+
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
+ if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
+ goto win;
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
+ if (m32c_mode_dependent_address (ADDR)) \
+ goto LABEL;
+
+#define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
+
+/* Condition Code Status */
+
+#define REVERSIBLE_CC_MODE(MODE) 1
+
+/* Describing Relative Costs of Operations */
+
+#define REGISTER_MOVE_COST(MODE,FROM,TO) \
+ m32c_register_move_cost (MODE, FROM, TO)
+#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
+ m32c_memory_move_cost (MODE, CLASS, IN)
+
+/* Dividing the Output into Sections (Texts, Data, ...) */
+
+#define TEXT_SECTION_ASM_OP ".text"
+#define DATA_SECTION_ASM_OP ".data"
+#define BSS_SECTION_ASM_OP ".bss"
+
+/* The Overall Framework of an Assembler File */
+
+#define ASM_COMMENT_START ";"
+#define ASM_APP_ON ""
+#define ASM_APP_OFF ""
+
+/* Output and Generation of Labels */
+
+#define GLOBAL_ASM_OP "\t.global\t"
+
+/* Output of Assembler Instructions */
+
+#define REGISTER_NAMES { \
+ "r0", "r2", "r1", "r3", \
+ "a0", "a1", "sb", "fb", "sp", \
+ "pc", "flg", "argp", \
+ "mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \
+}
+
+#define ADDITIONAL_REGISTER_NAMES { \
+ {"r0l", 0}, \
+ {"r1l", 2}, \
+ {"r0r2", 0}, \
+ {"r1r3", 2}, \
+ {"a0a1", 4}, \
+ {"r0r2r1r3", 0} }
+
+#define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
+#define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
+#define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
+
+#undef USER_LABEL_PREFIX
+#define USER_LABEL_PREFIX "_"
+
+#define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
+#define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
+
+/* Output of Dispatch Tables */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
+ fprintf (S, "\t.word L%d\n", V)
+
+/* Assembler Commands for Exception Regions */
+
+#define DWARF_CIE_DATA_ALIGNMENT -1
+
+/* Assembler Commands for Alignment */
+
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
+ fprintf (STREAM, "\t.p2align\t%d\n", POWER);
+
+/* Controlling Debugging Information Format */
+
+#define DWARF2_ADDR_SIZE 4
+
+/* Miscellaneous Parameters */
+
+#define HAS_LONG_COND_BRANCH false
+#define HAS_LONG_UNCOND_BRANCH true
+#define CASE_VECTOR_MODE SImode
+#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
+
+#define MOVE_MAX 4
+#define TRULY_NOOP_TRUNCATION(op,ip) 1
+
+/* 16 or 24 bit pointers */
+#define Pmode (TARGET_A16 ? HImode : PSImode)
+#define FUNCTION_MODE QImode
+
+#define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
+
+#endif
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+(define_constants
+ [(R0_REGNO 0)
+ (R2_REGNO 1)
+ (R1_REGNO 2)
+ (R3_REGNO 3)
+
+ (A0_REGNO 4)
+ (A1_REGNO 5)
+ (SB_REGNO 6)
+ (FB_REGNO 7)
+
+ (SP_REGNO 8)
+ (PC_REGNO 9)
+ (FLG_REGNO 10)
+ (MEM0_REGNO 12)
+ (MEM7_REGNO 19)
+ ])
+
+(define_constants
+ [(UNS_PROLOGUE_END 1)
+ (UNS_EPILOGUE_START 2)
+ (UNS_EH_EPILOGUE 3)
+ (UNS_PUSHM 4)
+ (UNS_POPM 5)
+ ])
+
+(define_insn "nop"
+ [(const_int 0)]
+ ""
+ "nop")
+
+;; n = no change, x = clobbered. The first 16 values are chosen such
+;; that the enum has one bit set for each flag.
+(define_attr "flags" "x,c,z,zc,s,sc,sz,szc,o,oc,oz,ozc,os,osc,osz,oszc,n" (const_string "n"))
+(define_asm_attributes [(set_attr "flags" "x")])
--- /dev/null
+; Target Options for R8C/M16C/M32C
+; Copyright (C) 2005
+; Free Software Foundation, Inc.
+; Contributed by Red Hat.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published
+; by the Free Software Foundation; either version 2, or (at your
+; option) any later version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING. If not, write to the Free
+; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+; 02110-1301, USA.
+
+msim
+Target
+-msim Use simulator runtime
+
+mcpu=r8c
+Target RejectNegative Var(target_cpu,'r') Init('r')
+-mcpu=r8c Compile code for R8C variants
+
+mcpu=m16c
+Target RejectNegative Var(target_cpu,'6')
+-mcpu=m16c Compile code for M16C variants
+
+mcpu=m32cm
+Target RejectNegative Var(target_cpu,'m')
+-mcpu=m32cm Compile code for M32CM variants
+
+mcpu=m32c
+Target RejectNegative Var(target_cpu,'3')
+-mcpu=m32c Compile code for M32C variants
+
+memregs=
+Target RejectNegative Joined Var(target_memregs_string)
+-memregs= Number of memreg bytes (default: 16, range: 0..16)
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; min, max
+
+(define_insn "sminqi3"
+ [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm,Raa,Raa")
+ (smin:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+ (match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))]
+ "TARGET_A24"
+ "min.b\t%2,%0"
+ )
+
+(define_insn "sminhi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+ (smin:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+ "TARGET_A24"
+ "min.w\t%2,%0"
+ )
+
+(define_insn "smaxqi3"
+ [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm,Raa,Raa")
+ (smax:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+ (match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))]
+ "TARGET_A24"
+ "max.b\t%2,%0"
+ )
+
+(define_insn "smaxhi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+ (smax:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+ (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+ "TARGET_A24"
+ "max.w\t%2,%0"
+ )
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; move, push, extend, etc.
+
+;; Be careful to never create an alternative that has memory as both
+;; src and dest, as that makes gcc think that mem-mem moves in general
+;; are supported. While the chip does support this, it only has two
+;; address registers and sometimes gcc requires more than that. One
+;; example is code like this: a = *b where both a and b are spilled to
+;; the stack.
+
+;; Match push/pop before mov.b for passing char as arg,
+;; e.g. stdlib/efgcvt.c.
+(define_insn "movqi_op"
+ [(set (match_operand:QI 0 "mra_qi_operand"
+ "=Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
+ (match_operand:QI 1 "mrai_qi_operand"
+ "iRqi*Rmm, iRqiSd*Rmm, >, iRqi*Rmm, SdSs, i"))]
+ "m32c_mov_ok (operands, QImode)"
+ "@
+ mov.b\t%1,%0
+ push.b\t%1
+ pop.b\t%0
+ mov.b\t%1,%0
+ mov.b\t%1,%0
+ mov.b\t%1,%0"
+ [(set_attr "flags" "sz,*,*,sz,sz,sz")]
+ )
+
+(define_expand "movqi"
+ [(set (match_operand:QI 0 "mra_qi_operand" "=RqiSd*Rmm")
+ (match_operand:QI 1 "mrai_qi_operand" "iRqiSd*Rmm"))]
+ ""
+ "if (m32c_prepare_move (operands, QImode)) DONE;"
+ )
+
+
+(define_insn "movhi_op"
+ [(set (match_operand:HI 0 "nonimmediate_operand"
+ "=Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
+ (match_operand:HI 1 "general_operand"
+ "iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
+ "m32c_mov_ok (operands, HImode)"
+ "@
+ mov.w\t%1,%0
+ mov.w\t%1,%0
+ mov.w\t%1,%0
+ ldc\t%1,%0
+ stc\t%1,%0
+ push.w\t%1
+ pop.w\t%0
+ pushc\t%1
+ popc\t%0"
+ [(set_attr "flags" "sz,sz,sz,*,*,*,*,*,*")]
+ )
+
+(define_expand "movhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=RhiSd*Rmm")
+ (match_operand:HI 1 "general_operand" "iRhiSd*Rmm"))]
+ ""
+ "if (m32c_prepare_move (operands, HImode)) DONE;"
+ )
+
+
+(define_insn "movpsi_op"
+ [(set (match_operand:PSI 0 "nonimmediate_operand"
+ "=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, Rsi*Rmm")
+ (match_operand:PSI 1 "general_operand"
+ "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rsi*Rmm, Rcl, >, >"))]
+ "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
+ "@
+ mov.l:s\t%1,%0
+ mov.l\t%1,%0
+ ldc\t%1,%0
+ stc\t%1,%0
+ push.l\t%1
+ pushc\t%1
+ popc\t%0
+ #"
+ [(set_attr "flags" "sz,sz,*,*,*,*,*,*")]
+ )
+
+
+;; The intention here is to combine the add with the move to create an
+;; indexed move. GCC doesn't always figure this out itself.
+
+(define_mode_macro QHSI [QI HI SI])
+(define_mode_macro HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
+
+(define_peephole2
+ [(set (match_operand:HPSI 0 "register_operand" "")
+ (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
+ (match_operand:HPSI 2 "immediate_operand" "")))
+ (set (match_operand:QHSI 3 "nonimmediate_operand" "")
+ (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
+ "REGNO (operands[0]) == REGNO (operands[1])
+ && REGNO (operands[0]) == REGNO (operands[4])
+ && dead_or_set_p (peep2_next_insn (1), operands[4])
+ && ! reg_mentioned_p (operands[0], operands[3])"
+ [(set (match_dup 3)
+ (mem:QHSI (plus:HPSI (match_dup 1)
+ (match_dup 2))))]
+ "")
+
+(define_peephole2
+ [(set (match_operand:HPSI 0 "register_operand" "")
+ (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
+ (match_operand:HPSI 2 "immediate_operand" "")))
+ (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
+ (match_operand:QHSI 3 "general_operand" ""))]
+ "REGNO (operands[0]) == REGNO (operands[1])
+ && REGNO (operands[0]) == REGNO (operands[4])
+ && dead_or_set_p (peep2_next_insn (1), operands[4])
+ && ! reg_mentioned_p (operands[0], operands[3])"
+ [(set (mem:QHSI (plus:HPSI (match_dup 1)
+ (match_dup 2)))
+ (match_dup 3))]
+ "")
+
+
+; Some PSI moves must be split.
+(define_split
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "")
+ (match_operand:PSI 1 "general_operand" ""))]
+ "reload_completed && m32c_split_psi_p (operands)"
+ [(set (match_dup 2)
+ (match_dup 3))
+ (set (match_dup 4)
+ (match_dup 5))]
+ "m32c_split_move (operands, PSImode, 3);"
+ )
+
+(define_expand "movpsi"
+ [(set (match_operand:PSI 0 "mras_operand" "")
+ (match_operand:PSI 1 "mrasi_operand" ""))]
+ ""
+ "if (m32c_prepare_move (operands, PSImode)) DONE;"
+ )
+
+
+
+(define_expand "movsi"
+ [(set (match_operand:SI 0 "mras_operand" "=RsiSd*Rmm")
+ (match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm"))]
+ ""
+ "if (m32c_split_move (operands, SImode, 0)) DONE;"
+ )
+
+; All SI moves are split if TARGET_A16
+(define_insn_and_split "movsi_splittable"
+ [(set (match_operand:SI 0 "mras_operand" "=Rsi<*Rmm,RsiSd*Rmm")
+ (match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm,iRsi>*Rmm"))]
+ "TARGET_A16"
+ "#"
+ "TARGET_A16 && reload_completed"
+ [(pc)]
+ "m32c_split_move (operands, SImode, 1); DONE;"
+ )
+
+; The movsi pattern doesn't always match because sometimes the modes
+; don't match.
+(define_insn "push_a01_l"
+ [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ (match_operand 0 "a_operand" ""))]
+ ""
+ "push.l\t%0"
+ )
+
+(define_insn "movsi_24"
+ [(set (match_operand:SI 0 "mras_operand" "=Rsi*Rmm, Sd, RsiSd*Rmm, <")
+ (match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
+ "TARGET_A24"
+ "@
+ mov.l\t%1,%0
+ mov.l\t%1,%0
+ #
+ push.l\t%1"
+ )
+
+(define_expand "movdi"
+ [(set (match_operand:DI 0 "mras_operand" "=RdiSd*Rmm")
+ (match_operand:DI 1 "mrasi_operand" "iRdiSd*Rmm"))]
+ ""
+ "if (m32c_split_move (operands, DImode, 0)) DONE;"
+ )
+
+(define_insn_and_split "movdi_splittable"
+ [(set (match_operand:DI 0 "mras_operand" "=Rdi<*Rmm,RdiSd*Rmm")
+ (match_operand:DI 1 "mrasi_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
+ ""
+ "#"
+ "reload_completed"
+ [(pc)]
+ "m32c_split_move (operands, DImode, 1); DONE;"
+ )
+
+
+
+
+(define_insn "pushqi"
+ [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
+ ""
+ "push.b\t%0"
+ )
+
+(define_expand "pushhi"
+ [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ (match_operand:HI 0 "" ""))]
+ ""
+ "if (TARGET_A16)
+ gen_pushhi_16 (operands[0]);
+ else
+ gen_pushhi_24 (operands[0]);
+ DONE;"
+ )
+
+(define_insn "pushhi_16"
+ [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
+ (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
+ "TARGET_A16"
+ "@
+ push.w\t%0
+ pushc\t%0"
+ )
+
+(define_insn "pushhi_24"
+ [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
+ "TARGET_A24"
+ "push.w\t%0"
+ )
+
+;(define_insn "pushpi"
+; [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
+; (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
+; "TARGET_A24"
+; "@
+; push.l\t%0
+; pushc\t%0"
+; )
+
+(define_insn "pushsi"
+ [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
+ "TARGET_A24"
+ "push.l\t%0"
+ )
+
+(define_expand "pophi"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
+ (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
+ ""
+ "if (TARGET_A16)
+ gen_pophi_16 (operands[0]);
+ else
+ gen_pophi_24 (operands[0]);
+ DONE;"
+ )
+
+(define_insn "pophi_16"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
+ (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
+ "TARGET_A16"
+ "@
+ pop.w\t%0
+ popc\t%0"
+ )
+
+(define_insn "pophi_24"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
+ (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
+ "TARGET_A24"
+ "pop.w\t%0"
+ )
+
+(define_insn "poppsi"
+ [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
+ (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
+ "TARGET_A24"
+ "popc\t%0"
+ )
+
+
+;; Rhl used here as an HI-mode Rxl
+(define_insn "extendqihi2"
+[(set (match_operand:HI 0 "mra_operand" "=RhlSd*Rmm")
+ (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
+ ""
+ "exts.b\t%1"
+ [(set_attr "flags" "sz")]
+ )
+
+(define_insn "extendhisi2"
+ [(set (match_operand:SI 0 "r0123_operand" "=R03")
+ (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
+ ""
+ "*
+ if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
+ else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
+ [(set_attr "flags" "sz")]
+ )
+
+(define_insn "extendpsisi2"
+ [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
+ (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
+ ""
+ "; expand psi %1 to si %0"
+ )
+
+(define_insn "zero_extendpsisi2"
+ [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
+ (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
+ ""
+ "; expand psi %1 to si %0"
+ )
+
+(define_insn "zero_extendhipsi2"
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "=Raa")
+ (truncate:PSI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "Rhi"))))]
+ ""
+ "mov.w\t%1,%0"
+ )
+
+(define_insn "zero_extendhisi2"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=RsiSd")
+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
+ ""
+ "mov.w\t#0,%H0"
+ )
+
+(define_insn "zero_extendqihi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=RsiRaaSd*Rmm")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
+ ""
+ "and.w\t#255,%0"
+ )
+
+(define_insn "truncsipsi2_16"
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
+ (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
+ "TARGET_A16"
+ "@
+ ; no-op trunc si %1 to psi %0
+ #
+ ldc\t%1,%0
+ stc\t%1,%0"
+ )
+
+(define_insn "trunchiqi2"
+ [(set (match_operand:QI 0 "mra_qi_operand" "=RqiRmmSd")
+ (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
+ ""
+ "; no-op trunc hi %1 to qi %0"
+ )
+
+(define_insn "truncsipsi2_24"
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
+ (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
+ "TARGET_A24"
+ "@
+ ; no-op trunc si %1 to psi %0
+ mov.l\t%1,%0
+ ldc\t%1,%0
+ stc\t%1,%0"
+ )
+
+(define_expand "truncsipsi2"
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
+ (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
+ ""
+ ""
+ )
+
+(define_expand "reload_inqi"
+ [(set (match_operand:QI 2 "" "=&Rqi")
+ (match_operand:QI 1 "" ""))
+ (set (match_operand:QI 0 "" "")
+ (match_dup 2))
+ ]
+ ""
+ "")
+
+(define_expand "reload_outqi"
+ [(set (match_operand:QI 2 "" "=&Rqi")
+ (match_operand:QI 1 "" ""))
+ (set (match_operand:QI 0 "" "")
+ (match_dup 2))
+ ]
+ ""
+ "")
+
+(define_expand "reload_inhi"
+ [(set (match_operand:HI 2 "" "=&Rhi")
+ (match_operand:HI 1 "" ""))
+ (set (match_operand:HI 0 "" "")
+ (match_dup 2))
+ ]
+ ""
+ "")
+
+(define_expand "reload_outhi"
+ [(set (match_operand:HI 2 "" "=&Rhi")
+ (match_operand:HI 1 "" ""))
+ (set (match_operand:HI 0 "" "")
+ (match_dup 2))
+ ]
+ ""
+ "")
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; multiply and divide
+
+; Here is the pattern for the const_int.
+(define_insn "mulqihi3_c"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+ (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
+ (match_operand 2 "immediate_operand" "i,i")))]
+ ""
+ "mul.b\t%2,%1"
+)
+
+; Here is the pattern for registers and such.
+(define_insn "mulqihi3_r"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+ (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+ (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
+ ""
+ "mul.b\t%2,%1"
+)
+
+; Don't try to sign_extend a const_int. Same for all other multiplies.
+(define_expand "mulqihi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+ (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+ (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
+ ""
+ "{ if (GET_MODE (operands[2]) != VOIDmode)
+ operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
+)
+
+(define_insn "umulqihi3_c"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+ (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
+ (match_operand 2 "immediate_operand" "i,i")))]
+ ""
+ "mulu.b\t%U2,%1"
+)
+
+(define_insn "umulqihi3_r"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+ (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+ (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
+ ""
+ "mulu.b\t%U2,%1"
+)
+
+(define_expand "umulqihi3"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+ (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+ (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
+ ""
+ "{ if (GET_MODE (operands[2]) != VOIDmode)
+ operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
+)
+
+(define_insn "mulhisi3_c"
+ [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
+ (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
+ (match_operand 2 "immediate_operand" "i,i")))]
+ ""
+ "mul.w\t%2,%1"
+)
+
+(define_insn "mulhisi3_r"
+ [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+ (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
+ (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
+ ""
+ "mul.w\t%2,%1"
+)
+
+(define_expand "mulhisi3"
+ [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+ (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
+ (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
+ ""
+ "{ if (GET_MODE (operands[2]) != VOIDmode)
+ operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
+)
+
+(define_insn "umulhisi3_c"
+ [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
+ (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
+ (match_operand 2 "immediate_operand" "i,i")))]
+ ""
+ "mulu.w\t%u2,%1"
+)
+
+(define_insn "umulhisi3_r"
+ [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+ (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
+ (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
+ ""
+ "mulu.w\t%u2,%1"
+)
+
+(define_expand "umulhisi3"
+ [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+ (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
+ (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
+ ""
+ "{ if (GET_MODE (operands[2]) != VOIDmode)
+ operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
+)
+
+
+; GCC expects to be able to multiply pointer-sized integers too, but
+; fortunately it only multiplies by powers of two.
+(define_insn "mulpsi3"
+ [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
+ (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
+ (match_operand 2 "const_int_operand" "Ilb")))]
+ "TARGET_A24"
+ "shl.l\t%b2,%0"
+ [(set_attr "flags" "szc")]
+ )
+
+
+
+(define_expand "divmodqi4"
+ [(set (match_dup 4)
+ (sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
+ (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
+ (div:QI (match_dup 4)
+ (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+ (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
+ (mod:QI (match_dup 4) (match_dup 2)))
+ ])]
+ "0"
+ "operands[4] = gen_reg_rtx (HImode);"
+ )
+
+(define_insn "divmodqi4_n"
+ [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
+ (div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
+ (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+ (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
+ (mod:QI (match_dup 1) (match_dup 2)))
+ ]
+ "0"
+ "div.b\t%2"
+ )
+
+(define_expand "udivmodqi4"
+ [(set (match_dup 4)
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
+ (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
+ (udiv:QI (match_dup 4)
+ (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+ (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
+ (umod:QI (match_dup 4) (match_dup 2)))
+ ])]
+ "0"
+ "operands[4] = gen_reg_rtx (HImode);"
+ )
+
+(define_insn "udivmodqi4_n"
+ [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
+ (udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
+ (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+ (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
+ (umod:QI (match_dup 1) (match_dup 2)))
+ ]
+ "0"
+ "divu.b\t%2"
+ )
+
+(define_expand "divmodhi4"
+ [(set (match_dup 4)
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
+ (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
+ (div:HI (match_dup 4)
+ (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
+ (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
+ (mod:HI (match_dup 4) (match_dup 2)))
+ ])]
+ ""
+ "operands[4] = gen_reg_rtx (SImode);"
+ )
+
+(define_insn "divmodhi4_n"
+ [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
+ (div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
+ (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
+ (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
+ (mod:HI (match_dup 1) (match_dup 2)))
+ ]
+ ""
+ "div.w\t%2"
+ )
+
+(define_expand "udivmodhi4"
+ [(set (match_dup 4)
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
+ (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
+ (udiv:HI (match_dup 4)
+ (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
+ (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
+ (umod:HI (match_dup 4) (match_dup 2)))
+ ])]
+ ""
+ "operands[4] = gen_reg_rtx (SImode);"
+ )
+
+(define_insn "udivmodhi4_n"
+ [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
+ (udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
+ (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
+ (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
+ (umod:HI (match_dup 1) (match_dup 2)))
+ ]
+ ""
+ "divu.w\t%2"
+ )
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; Predicates
+
+; TRUE if the operand is a pseudo-register.
+(define_predicate "m32c_pseudo"
+ (ior (and (match_code "reg")
+ (match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER"))
+ (and (match_code "subreg")
+ (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
+ (match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER")))))
+
+
+; Returning true causes many predicates to NOT match. We allow
+; subregs for type changing, but not for size changing.
+(define_predicate "m32c_wide_subreg"
+ (and (match_code "subreg")
+ (not (match_operand 0 "m32c_pseudo")))
+ {
+ unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op));
+ unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0)));
+ sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ return sizeo != sizei;
+ })
+
+; TRUE for r0 through r3, or a pseudo that reload could put in r0
+; through r3 (likewise for the next couple too)
+(define_predicate "r0123_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_code "reg")
+ (match_test "REGNO(op) <= R3_REGNO"))))
+
+; TRUE for r0
+(define_predicate "m32c_r0_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_code "reg")
+ (match_test "REGNO(op) == R0_REGNO"))))
+
+; TRUE for r1
+(define_predicate "m32c_r1_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_code "reg")
+ (match_test "REGNO(op) == R1_REGNO"))))
+
+; TRUE for r2
+(define_predicate "m32c_r2_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_code "reg")
+ (match_test "REGNO(op) == R2_REGNO"))))
+
+; TRUE for any general operand except r2.
+(define_predicate "m32c_notr2_operand"
+ (and (match_operand 0 "general_operand")
+ (ior (not (match_code "reg"))
+ (match_test "REGNO(op) != R2_REGNO"))))
+
+; TRUE for the stack pointer.
+(define_predicate "m32c_sp_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_code "reg")
+ (match_test "REGNO(op) == SP_REGNO"))))
+
+; TRUE for control registers.
+(define_predicate "cr_operand"
+ (match_code "reg")
+ "return (REGNO (op) >= SB_REGNO
+ && REGNO (op) <= FLG_REGNO);")
+
+; TRUE for $a0 or $a1.
+(define_predicate "a_operand"
+ (match_code "reg")
+ "return (REGNO (op) == A0_REGNO
+ || REGNO (op) == A1_REGNO);")
+
+; TRUE for r0 through r3, or a0 or a1.
+(define_predicate "ra_operand"
+ (and (and (match_operand 0 "register_operand" "")
+ (not (match_operand 1 "cr_operand" "")))
+ (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+; Likewise, plus TRUE for memory references.
+(define_predicate "mra_operand"
+ (and (and (match_operand 0 "nonimmediate_operand" "")
+ (not (match_operand 1 "cr_operand" "")))
+ (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+; Likewise, plus TRUE for subregs.
+(define_predicate "mras_operand"
+ (and (match_operand 0 "nonimmediate_operand" "")
+ (not (match_operand 1 "cr_operand" ""))))
+
+; TRUE for memory, r0..r3, a0..a1, or immediates.
+(define_predicate "mrai_operand"
+ (and (and (match_operand 0 "general_operand" "")
+ (not (match_operand 1 "cr_operand" "")))
+ (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+; Likewise, plus true for subregs.
+(define_predicate "mrasi_operand"
+ (and (match_operand 0 "general_operand" "")
+ (not (match_operand 1 "cr_operand" ""))))
+
+; TRUE for r0..r3 or memory.
+(define_predicate "mr_operand"
+ (and (match_operand 0 "mra_operand" "")
+ (not (match_operand 1 "a_operand" ""))))
+
+; TRUE for r1h. This complicated since r1h isn't a register GCC
+; normally knows about.
+(define_predicate "r1h_operand"
+ (match_code "zero_extract")
+ {
+ rtx reg = XEXP (op, 0);
+ rtx size = XEXP (op, 1);
+ rtx pos = XEXP (op, 2);
+ return (GET_CODE (reg) == REG
+ && REGNO (reg) == R1_REGNO
+ && GET_CODE (size) == CONST_INT
+ && INTVAL (size) == 8
+ && GET_CODE (pos) == CONST_INT
+ && INTVAL (pos) == 8);
+ })
+
+; TRUE if we can shift by this amount. Constant shift counts have a
+; limited range.
+(define_predicate "shiftcount_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_operand 2 "const_int_operand" "")
+ (match_test "-8 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 8"))))
+
+; TRUE for r0..r3, a0..a1, or sp.
+(define_predicate "mra_or_sp_operand"
+ (and (ior (match_operand 0 "mra_operand")
+ (match_operand 1 "m32c_sp_operand"))
+ (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+
+; TRUE for r2 or r3.
+(define_predicate "m32c_r2r3_operand"
+ (ior (and (match_code "reg")
+ (ior (match_test "REGNO(op) == R2_REGNO")
+ (match_test "REGNO(op) == R3_REGNO")))
+ (and (match_code "subreg")
+ (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
+
+; Likewise, plus TRUE for a0..a1.
+(define_predicate "m32c_r2r3a_operand"
+ (ior (match_operand 0 "m32c_r2r3_operand" "")
+ (match_operand 0 "a_operand" "")))
+
+; These two are only for movqi - no subreg limit
+(define_predicate "mra_qi_operand"
+ (and (and (match_operand 0 "nonimmediate_operand" "")
+ (not (match_operand 1 "cr_operand" "")))
+ (not (match_operand 1 "m32c_r2r3a_operand" ""))))
+
+(define_predicate "mrai_qi_operand"
+ (and (and (match_operand 0 "general_operand" "")
+ (not (match_operand 1 "cr_operand" "")))
+ (not (match_operand 1 "m32c_r2r3a_operand" ""))))
+
+; TRUE for comparisons we support.
+(define_predicate "m32c_cmp_operator"
+ (match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu"))
+
+; TRUE for mem0
+(define_predicate "m32c_mem0_operand"
+ (ior (match_operand 0 "m32c_pseudo" "")
+ (and (match_code "reg")
+ (match_test "REGNO(op) == MEM0_REGNO"))))
+
+; TRUE for things the call patterns can return.
+(define_predicate "m32c_return_operand"
+ (ior (match_operand 0 "m32c_r0_operand")
+ (ior (match_operand 0 "m32c_mem0_operand")
+ (match_code "parallel"))))
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; Prologue and epilogue patterns
+
+(define_expand "prologue"
+ [(const_int 1)]
+ ""
+ "m32c_emit_prologue(); DONE;"
+ )
+
+; For the next two, operands[0] is the amount of stack space we want
+; to reserve.
+
+; We assume dwarf2out will process each set in sequence.
+(define_insn "prologue_enter_16"
+ [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
+ (reg:HI FB_REGNO))
+ (set (reg:HI FB_REGNO)
+ (reg:HI SP_REGNO))
+ (set (reg:HI SP_REGNO)
+ (minus:HI (reg:HI SP_REGNO)
+ (match_operand 0 "const_int_operand" "i")))
+ ]
+ "TARGET_A16"
+ "enter\t%0"
+ )
+
+(define_insn "prologue_enter_24"
+ [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ (reg:SI FB_REGNO))
+ (set (reg:PSI FB_REGNO)
+ (reg:PSI SP_REGNO))
+ (set (reg:PSI SP_REGNO)
+ (minus:PSI (reg:PSI SP_REGNO)
+ (match_operand 0 "const_int_operand" "i")))
+ ]
+ "TARGET_A24"
+ "enter\t%0"
+ )
+
+; Just a comment, for debugging the assembler output.
+(define_insn "prologue_end"
+ [(unspec_volatile [(const_int 0)] UNS_PROLOGUE_END)]
+ ""
+ "; end of prologue"
+ )
+
+
+
+(define_expand "epilogue"
+ [(const_int 1)]
+ ""
+ "m32c_emit_epilogue(); DONE;"
+ )
+
+(define_expand "eh_return"
+ [(match_operand:PSI 0 "" "")]
+ ""
+ "m32c_emit_eh_epilogue(operands[0]); DONE;"
+ )
+
+(define_insn "eh_epilogue"
+ [(set (pc)
+ (unspec_volatile [(match_operand 0 "m32c_r1_operand" "")
+ (match_operand 1 "m32c_r0_operand" "")
+ ] UNS_EH_EPILOGUE))]
+ ""
+ "jmp.a\t__m32c_eh_return"
+ )
+
+(define_insn "epilogue_exitd"
+ [(set (reg:PSI SP_REGNO)
+ (reg:PSI FB_REGNO))
+ (set (reg:PSI FB_REGNO)
+ (mem:PSI (reg:PSI SP_REGNO)))
+ (set (reg:PSI SP_REGNO)
+ (plus:PSI (reg:PSI SP_REGNO)
+ (match_operand 0 "const_int_operand" "i")))
+ (return)
+ ]
+ ""
+ "exitd"
+ )
+
+(define_insn "epilogue_reit"
+ [(set (reg:PSI SP_REGNO)
+ (plus:PSI (reg:PSI SP_REGNO)
+ (match_operand 0 "const_int_operand" "i")))
+ (return)
+ ]
+ ""
+ "reit"
+ )
+
+(define_insn "epilogue_rts"
+ [(return)
+ ]
+ ""
+ "rts"
+ )
+
+(define_insn "epilogue_start"
+ [(unspec_volatile [(const_int 0)] UNS_EPILOGUE_START)]
+ ""
+ "; start of epilogue"
+ )
+
+
+; These are used by the prologue/epilogue code.
+
+(define_insn "pushm"
+ [(unspec [(match_operand 0 "const_int_operand" "i")] UNS_PUSHM)]
+ ""
+ "pushm\t%p0")
+
+(define_insn "popm"
+ [(unspec [(match_operand 0 "const_int_operand" "i")] UNS_POPM)]
+ ""
+ "popm\t%p0")
--- /dev/null
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the Free
+;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+;; 02110-1301, USA.
+
+;; bit shifting
+
+; Shifts are unusual for m32c. We only support shifting in one
+; "direction" but the shift count is signed. Also, immediate shift
+; counts have a limited range, and variable shift counts have to be in
+; $r1h which GCC normally doesn't even know about.
+
+; Other than compensating for the above, the patterns below are pretty
+; straightforward.
+
+(define_insn "ashlqi3_i"
+ [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
+ (ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
+ (match_operand:QI 2 "mrai_operand" "In4,R1w")))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ sha.b\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.b\tr1h,%0"
+ )
+
+(define_insn "ashrqi3_i"
+ [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
+ (ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ sha.b\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.b\tr1h,%0"
+ )
+
+(define_insn "lshlqi3_i"
+ [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
+ (lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ shl.b\t%2,%0
+ mov.b\tr1l,r1h\n\tshl.b\tr1h,%0"
+ )
+
+
+(define_expand "ashlqi3"
+ [(parallel [(set (match_operand:QI 0 "mra_operand" "")
+ (ashift:QI (match_operand:QI 1 "mra_operand" "")
+ (match_operand:QI 2 "general_operand" "")))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, 1, 4))
+ DONE;"
+ )
+
+(define_expand "ashrqi3"
+ [(parallel [(set (match_operand:QI 0 "mra_operand" "")
+ (ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
+ (neg:QI (match_operand:QI 2 "general_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+(define_expand "lshrqi3"
+ [(parallel [(set (match_operand:QI 0 "mra_operand" "")
+ (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
+ (neg:QI (match_operand:QI 2 "general_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+(define_insn "ashlhi3_i"
+ [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
+ (ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
+ (match_operand:QI 2 "mrai_operand" "In4,R1w")))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ sha.w\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.w\tr1h,%0"
+ )
+
+(define_insn "ashrhi3_i"
+ [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
+ (ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ sha.w\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.w\tr1h,%0"
+ )
+
+(define_insn "lshlhi3_i"
+ [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
+ (lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ shl.w\t%2,%0
+ mov.b\tr1l,r1h\n\tshl.w\tr1h,%0"
+ )
+
+
+(define_expand "ashlhi3"
+ [(parallel [(set (match_operand:HI 0 "mra_operand" "")
+ (ashift:HI (match_operand:HI 1 "mra_operand" "")
+ (match_operand:QI 2 "general_operand" "")))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, 1, 4))
+ DONE;"
+ )
+
+(define_expand "ashrhi3"
+ [(parallel [(set (match_operand:HI 0 "mra_operand" "")
+ (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
+ (neg:QI (match_operand:QI 2 "general_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+(define_expand "lshrhi3"
+ [(parallel [(set (match_operand:HI 0 "mra_operand" "")
+ (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
+ (neg:QI (match_operand:QI 2 "general_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+
+
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+
+(define_insn "ashlpsi3_i"
+ [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
+ (ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
+ (match_operand:QI 2 "mrai_operand" "In4,R1w")))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ "TARGET_A24"
+ "@
+ sha.l\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.l\tr1h,%0"
+ )
+
+(define_insn "ashrpsi3_i"
+ [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
+ (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ "TARGET_A24"
+ "@
+ sha.l\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.l\tr1h,%0"
+ )
+
+(define_insn "lshlpsi3_i"
+ [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
+ (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ "TARGET_A24"
+ "@
+ shl.l\t%2,%0
+ mov.b\tr1l,r1h\n\tshl.l\tr1h,%0"
+ )
+
+
+(define_expand "ashlpsi3"
+ [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
+ (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
+ (match_operand:QI 2 "mrai_operand" "")))
+ (clobber (match_scratch:HI 3 ""))])]
+ "TARGET_A24"
+ "if (m32c_prepare_shift (operands, 1, 4))
+ DONE;"
+ )
+
+(define_expand "ashrpsi3"
+ [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
+ (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
+ (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ "TARGET_A24"
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+(define_expand "lshrpsi3"
+ [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
+ (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
+ (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ "TARGET_A24"
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+
+
+(define_insn "ashlsi3_i"
+ [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+ (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
+ (match_operand:QI 2 "mrai_operand" "In4,R1w")))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ sha.l\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.l\tr1h,%0"
+ )
+
+(define_insn "ashrsi3_i"
+ [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+ (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ sha.l\t%2,%0
+ mov.b\tr1l,r1h\n\tsha.l\tr1h,%0"
+ )
+
+(define_insn "lshlsi3_i"
+ [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+ (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
+ (neg:QI (match_operand:QI 2 "mrai_operand" "In4,R1w"))))
+ (clobber (match_scratch:HI 3 "=X,R1w"))]
+ ""
+ "@
+ shl.l\t%2,%0
+ mov.b\tr1l,r1h\n\tshl.l\tr1h,%0"
+ )
+
+
+(define_expand "ashlsi3"
+ [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
+ (ashift:SI (match_operand:SI 1 "r0123_operand" "")
+ (match_operand:QI 2 "mrai_operand" "")))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, 1, 4))
+ DONE;"
+ )
+
+(define_expand "ashrsi3"
+ [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
+ (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
+ (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, -1, 4))
+ DONE;"
+ )
+
+(define_expand "lshrsi3"
+ [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
+ (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
+ (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
+ (clobber (match_scratch:HI 3 ""))])]
+ ""
+ "if (m32c_prepare_shift (operands, -1, 5))
+ DONE;"
+ )
--- /dev/null
+# Target Makefile Fragment for R8C/M16C/M32C
+# Copyright (C) 2005
+# Free Software Foundation, Inc.
+# Contributed by Red Hat.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 2, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING. If not, write to the Free
+# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+# 02110-1301, USA.
+
+LIB1ASMSRC = m32c/m32c-lib1.S
+
+LIB1ASMFUNCS = \
+ __m32c_memregs \
+ __m32c_eh_return \
+ __m32c_mulsi3 \
+ __m32c_cmpsi2 \
+ __m32c_ucmpsi2 \
+ __m32c_jsri16
+
+LIB2FUNCS_EXTRA = $(srcdir)/config/m32c/m32c-lib2.c
+
+# floating point emulation libraries
+
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+ echo '#define FLOAT' > fp-bit.c
+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+ cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+# target-specific files
+
+md_file = md
+
+MD_FILES = m32c predicates addsub bitops cond jump minmax mov muldiv prologue shift
+
+# Doing it this way lets the gen* programs report the right line numbers.
+
+md : $(MD_FILES:%=$(srcdir)/config/m32c/%.md) $(srcdir)/config/m32c/t-m32c
+ for md in $(MD_FILES); do \
+ echo "(include \"$(srcdir)/config/m32c/$$md.md\")"; \
+ done > md
+
+m32c-pragma.o: $(srcdir)/config/m32c/m32c-pragma.c $(RTL_H) $(TREE_H) $(CONFIG_H)
+ $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+
+# We support four CPU series, but R8C and M16C share one multilib, and
+# M32C and M32CM share another.
+
+MULTILIB_OPTIONS = mcpu=m32cm
+MULTILIB_DIRNAMES = m32cm
+MULTILIB_MATCHES = mcpu?m32cm=mcpu?m32c mcpu?r8c=mcpu?m16c
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
Mo DeJong for GCJ and libgcj bug fixes.
@item
-DJ Delorie for the DJGPP port, build and libiberty maintenance, and
-various bug fixes.
+DJ Delorie for the DJGPP port, build and libiberty maintenance,
+various bug fixes, and the M32C port.
@item
Arnaud Desitter for helping to debug gfortran.
@item interrupt
@cindex interrupt handler functions
-Use this attribute on the ARM, AVR, C4x, M32R/D and Xstormy16 ports to indicate
-that the specified function is an interrupt handler. The compiler will
-generate function entry and exit sequences suitable for use in an
-interrupt handler when this attribute is present.
+Use this attribute on the ARM, AVR, C4x, M32C, M32R/D and Xstormy16
+ports to indicate that the specified function is an interrupt handler.
+The compiler will generate function entry and exit sequences suitable
+for use in an interrupt handler when this attribute is present.
Note, interrupt handlers for the Blackfin, m68k, H8/300, H8/300H, H8S, and
SH processors can be specified via the @code{interrupt_handler} attribute.
@menu
* ARM Pragmas::
+* M32C Pragmas::
* RS/6000 and PowerPC Pragmas::
* Darwin Pragmas::
* Solaris Pragmas::
subsequent functions.
@end table
+@node M32C Pragmas
+@subsection M32C Pragmas
+
+@table @code
+@item memregs @var{number}
+@cindex pragma, memregs
+Overrides the command line option @code{-memregs=} for the current
+file. Use with care! This pragma must be before any function in the
+file, and mixing different memregs values in different objects may
+make them incompatible. This pragma is useful when a
+performance-critical function uses a memreg for temporary values,
+as it may allow you to reduce the number of memregs used.
+
+@end table
+
@node RS/6000 and PowerPC Pragmas
@subsection RS/6000 and PowerPC Pragmas
@item
@uref{#iq2000-x-elf,,iq2000-*-elf}
@item
+@uref{#m32c-x-elf,,m32c-*-elf}
+@item
@uref{#m32r-x-elf,,m32r-*-elf}
@item
@uref{#m6811-elf,,m6811-elf}
@html
<hr />
@end html
+@heading @anchor{m32c-x-elf}m32c-*-elf
+Renesas M32C processor.
+This configuration is intended for embedded systems.
+
+@html
+<hr />
+@end html
@heading @anchor{m32r-x-elf}m32r-*-elf
Renesas M32R processor.
This configuration is intended for embedded systems.
-mno-flush-trap -mflush-trap=@var{number} @gol
-G @var{num}}
+@emph{M32C Options}
+@gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}}
+
@emph{M680x0 Options}
@gccoptlist{-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol
-m68060 -mcpu32 -m5200 -m68881 -mbitfield -mc68000 -mc68020 @gol
* HPPA Options::
* i386 and x86-64 Options::
* IA-64 Options::
+* M32C Options::
* M32R/D Options::
* M680x0 Options::
* M68hc1x Options::
@end table
+@node M32C Options
+@subsection M32C Options
+@cindex M32C options
+
+@table @gcctabopt
+@item -mcpu=@var{name}
+@opindex mcpu=
+Select the CPU for which code is generated. @var{name} may be one of
+@samp{r8c} for the R8C/Tiny series, @samp{m16c} for the M16C (up to
+/60) series, @samp{m32cm} for the M16C/80 series, or @samp{m32c} for
+the M32C/80 series.
+
+@item -msim
+@opindex msim
+Specifies that the program will be run on the simulator. This causes
+an alternate runtime library to be linked in which supports, for
+example, file I/O. You must not use this option when generating
+programs that will run on real hardware; you must provide your own
+runtime library for whatever I/O functions are needed.
+
+@item -memregs=@var{number}
+@opindex memregs=
+Specifies the number of memory-based pseudo-registers GCC will use
+during code generation. These pseudo-registers will be used like real
+registers, so there is a tradeoff between GCC's ability to fit the
+code into available registers, and the performance penalty of using
+memory instead of registers. Note that all modules in a program must
+be compiled with the same value for this option. Because of that, you
+must not use this option with the default runtime libraries gcc
+builds.
+
+@end table
+
@node M32R/D Options
@subsection M32R/D Options
@cindex M32R/D options
Any SYMBOL_REF.
@end table
+@item M32C---@file{m32c.c}
+
+@item Rsp
+@itemx Rfb
+@itemx Rsb
+@samp{$sp}, @samp{$fb}, @samp{$sb}.
+
+@item Rcr
+Any control register, when they're 16 bits wide (nothing if control
+registers are 24 bits wide)
+
+@item Rcl
+Any control register, when they're 24 bits wide.
+
+@item R0w
+@itemx R1w
+@itemx R2w
+@itemx R3w
+$r0, $r1, $r2, $r3.
+
+@item R02
+$r0 or $r2, or $r2r0 for 32 bit values.
+
+@item R13
+$r1 or $r3, or $r3r1 for 32 bit values.
+
+@item Rdi
+A register that can hold a 64 bit value.
+
+@item Rhl
+$r0 or $r1 (registers with addressable high/low bytes)
+
+@item R23
+$r2 or $r3
+
+@item Raa
+Address registers
+
+@item Raw
+Address registers when they're 16 bits wide.
+
+@item Ral
+Address registers when they're 24 bits wide.
+
+@item Rqi
+Registers that can hold QI values.
+
+@item Rad
+Registers that can be used with displacements ($a0, $a1, $sb).
+
+@item Rsi
+Registers that can hold 32 bit values.
+
+@item Rhi
+Registers that can hold 16 bit values.
+
+@item Rhc
+Registers chat can hold 16 bit values, including all control
+registers.
+
+@item Rra
+$r0 through R1, plus $a0 and $a1.
+
+@item Rfl
+The flags register.
+
+@item Rmm
+The memory-based pseudo-registers $mem0 through $mem15.
+
+@item Rpi
+Registers that can hold pointers (16 bit registers for r8c, m16c; 24
+bit registers for m32cm, m32c).
+
+@item Rpa
+Matches multiple registers in a PARALLEL to form a larger register.
+Used to match function return values.
+
+@item Is3
+-8 @dots{} 7
+
+@item IS1
+-128 @dots{} 127
+
+@item IS2
+-32768 @dots{} 32767
+
+@item IU2
+0 @dots{} 65535
+
+@item In4
+-8 @dots{} -1 or 1 @dots{} 8
+
+@item In5
+-16 @dots{} -1 or 1 @dots{} 16
+
+@item In4
+-8 @dots{} -1 or 1 @dots{} 8
+
+@item IM2
+-65536 @dots{} -1
+
+@item Ilb
+An 8 bit value with exactly one bit set.
+
+@item Ilw
+A 16 bit value with exactly one bit set.
+
+@item Sd
+The common src/dest memory addressing modes.
+
+@item Sa
+Memory addressed using $a0 or $a1.
+
+@item Si
+Memory addressed with immediate addresses.
+
+@item Ss
+Memory addressed using the stack pointer ($sp).
+
+@item Sf
+Memory addressed using the frame base register ($fb).
+
+@item Ss
+Memory addressed using the small base register ($sb).
+
+@item S1
+$r1h
+
+
@item MIPS---@file{mips.h}
@table @code
@item d
projects / platform / upstream / gcc.git / commitdiff