+2011-12-13 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/mips/mips-cpus.def: Add Octeon2.
+ * config/mips/mips-tables.opt: Regenerate.
+ * config/mips/mips.md (define_attr "cpu"): Add Octeon2.
+ * config/mips/driver-native.c (host_detect_local_cpu): Support Octeon2 also.
+ * config/mips/octeon.md (octeon_arith): Add Octeon2.
+ (octeon_condmove): Likewise.
+ (octeon_load): Rename to ..
+ (octeon_load_o1): this.
+ (octeon_load_o2): New reserve.
+ (octeon_cop_o2): New reserve.
+ (octeon_store): Match Octeon2 also.
+ (octeon_brj): Rename to ..
+ (octeon_brj_o1): this.
+ (octeon_brj_o2): New reserve.
+ (octeon_imul3): Rename to ...
+ (octeon_imul3_o1): this.
+ (octeon_imul3_o2): New reserve.
+ (octeon_imul): Rename to ...
+ (octeon_imul_o1): this.
+ (octeon_imul_o2): New reserve.
+ (octeon_mfhilo): Rename to ...
+ (octeon_mfhilo_o1): This.
+ (octeon_mfhilo_o2): New reserve.
+ (octeon_imadd): Rename to ...
+ (octeon_imadd_o1): this.
+ (octeon_imadd_o2): New reserve.
+ (octeon_idiv): Rename to ..
+ (octeon_idiv_o1): This.
+ (octeon_idiv_o2_si): New reserve.
+ (octeon_idiv_o2_di): Likewise.
+ (octeon_unknown): Match Octeon2 also.
+ * config/mips/mips.c (mips_rtx_cost_data): Add Octeon2 cost data.
+ (mips_issue_rate): Octeon2 can issue 2 at a time.
+ * config/mips/mips.h (TARGET_OCTEON): Match Octeon2 also.
+ (TARGET_OCTEON2): New define.
+ (TUNE_OCTEON): Match Octeon2 also.
+
2011-12-13 Richard Henderson <rth@redhat.com>
* config/sparc/tso.h: New file.
(define_cpu_unit "octeon_mult" "octeon_mult")
(define_insn_reservation "octeon_arith" 1
- (and (eq_attr "cpu" "octeon")
+ (and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_condmove" 2
- (and (eq_attr "cpu" "octeon")
+ (and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "condmove"))
"octeon_pipe0 | octeon_pipe1")
-(define_insn_reservation "octeon_load" 2
+(define_insn_reservation "octeon_load_o1" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "load,prefetch,mtc,mfc"))
"octeon_pipe0")
+(define_insn_reservation "octeon_load_o2" 3
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "load,prefetch"))
+ "octeon_pipe0")
+
+;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency.
+;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now.
+(define_insn_reservation "octeon_cop_o2" 1
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "mtc,mfc"))
+ "octeon_pipe1")
+
(define_insn_reservation "octeon_store" 1
- (and (eq_attr "cpu" "octeon")
+ (and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "store"))
"octeon_pipe0")
-(define_insn_reservation "octeon_brj" 1
+(define_insn_reservation "octeon_brj_o1" 1
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "branch,jump,call,trap"))
"octeon_pipe0")
-(define_insn_reservation "octeon_imul3" 5
+(define_insn_reservation "octeon_brj_o2" 2
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "branch,jump,call,trap"))
+ "octeon_pipe1")
+
+(define_insn_reservation "octeon_imul3_o1" 5
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imul3,pop,clz"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
-(define_insn_reservation "octeon_imul" 2
+(define_insn_reservation "octeon_imul3_o2" 6
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "imul3,pop,clz"))
+ "octeon_pipe1 + octeon_mult")
+
+(define_insn_reservation "octeon_imul_o1" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imul,mthilo"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
-(define_insn_reservation "octeon_mfhilo" 5
+(define_insn_reservation "octeon_imul_o2" 1
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "imul,mthilo"))
+ "octeon_pipe1 + octeon_mult")
+
+(define_insn_reservation "octeon_mfhilo_o1" 5
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "mfhilo"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
-(define_insn_reservation "octeon_imadd" 4
+(define_insn_reservation "octeon_mfhilo_o2" 6
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "mfhilo"))
+ "octeon_pipe1 + octeon_mult")
+
+(define_insn_reservation "octeon_imadd_o1" 4
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imadd"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
-(define_insn_reservation "octeon_idiv" 72
+(define_insn_reservation "octeon_imadd_o2" 1
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "type" "imadd"))
+ "octeon_pipe1 + octeon_mult")
+
+(define_insn_reservation "octeon_idiv_o1" 72
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "idiv"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
+(define_insn_reservation "octeon_idiv_o2_si" 18
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "mode" "SI")
+ (eq_attr "type" "idiv"))
+ "octeon_pipe1 + octeon_mult, octeon_mult*17")
+
+(define_insn_reservation "octeon_idiv_o2_di" 35
+ (and (eq_attr "cpu" "octeon2")
+ (eq_attr "mode" "DI")
+ (eq_attr "type" "idiv"))
+ "octeon_pipe1 + octeon_mult, octeon_mult*34")
+
;; Assume both pipes are needed for unknown and multiple-instruction
;; patterns.
(define_insn_reservation "octeon_unknown" 1
- (and (eq_attr "cpu" "octeon")
+ (and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "unknown,multi"))
"octeon_pipe0 + octeon_pipe1")