DAG.getRegister(0, MVT::i16), // Segment.
Zero,
Chain};
- SDNode *Res = DAG.getMachineNode(X86::LOCK_OR32mi8, DL, MVT::i32,
+ SDNode *Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32,
MVT::Other, Ops);
return SDValue(Res, 1);
}
Zero,
Chain
};
- SDNode *Res = DAG.getMachineNode(X86::LOCK_OR32mi8, DL, MVT::i32,
+ SDNode *Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32,
MVT::Other, Ops);
return SDValue(Res, 1);
}
// If we have at least one (non-frame-index, non-RIP) register operand,
// and neither operand is load-dependent, we need to check the load.
- // Also handle explicit references to RSP as used by idempotent atomic
- // or with 0.
unsigned BaseReg = 0, IndexReg = 0;
if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
- BaseMO.getReg() != X86::RSP && BaseMO.getReg() != X86::NoRegister)
+ BaseMO.getReg() != X86::NoRegister)
BaseReg = BaseMO.getReg();
if (IndexMO.getReg() != X86::NoRegister)
IndexReg = IndexMO.getReg();
define void @idempotent_atomic(i32* %x) speculative_load_hardening {
; X64-LABEL: idempotent_atomic:
; X64: # %bb.0:
-; X64-NEXT: movq %rsp, %rax
-; X64-NEXT: movq $-1, %rcx
-; X64-NEXT: sarq $63, %rax
-; X64-NEXT: lock orl $0, -64(%rsp)
-; X64-NEXT: shlq $47, %rax
-; X64-NEXT: orq %rax, %rsp
+; X64-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
; X64-NEXT: retq
;
; X64-LFENCE-LABEL: idempotent_atomic:
; X64-LFENCE: # %bb.0:
-; X64-LFENCE-NEXT: lock orl $0, -64(%rsp)
+; X64-LFENCE-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
; X64-LFENCE-NEXT: retq
%tmp = atomicrmw or i32* %x, i32 0 seq_cst
ret void