drm/panfrost: Handle HW_ISSUE_TTRX_2968_TTRX_3162
authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Wed, 25 May 2022 14:57:47 +0000 (10:57 -0400)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Thu, 26 May 2022 13:53:01 +0000 (09:53 -0400)
Add handling for the HW_ISSUE_TTRX_2968_TTRX_3162 quirk. Logic ported
from kbase. kbase lists this workaround as used on Mali-G57.

Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220525145754.25866-3-alyssa.rosenzweig@collabora.com
drivers/gpu/drm/panfrost/panfrost_gpu.c
drivers/gpu/drm/panfrost/panfrost_issues.h
drivers/gpu/drm/panfrost/panfrost_regs.h

index aa89926..295bef2 100644 (file)
@@ -108,6 +108,9 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
                        quirks |= SC_LS_ALLOW_ATTR_TYPES;
        }
 
+       if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162))
+               quirks |= SC_VAR_ALGORITHM;
+
        if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
                quirks |= SC_TLS_HASH_ENABLE;
 
index 501a76c..41a714c 100644 (file)
@@ -125,6 +125,9 @@ enum panfrost_hw_issue {
         * kernel must fiddle with L2 caches to prevent data leakage */
        HW_ISSUE_TGOX_R1_1234,
 
+       /* Must set SC_VAR_ALGORITHM */
+       HW_ISSUE_TTRX_2968_TTRX_3162,
+
        HW_ISSUE_END
 };
 
index 0b6cd8f..accb4fa 100644 (file)
 #define SC_TLS_HASH_ENABLE             BIT(17)
 #define SC_LS_ATTR_CHECK_DISABLE       BIT(18)
 #define SC_ENABLE_TEXGRD_FLAGS         BIT(25)
+#define SC_VAR_ALGORITHM               BIT(29)
 /* End SHADER_CONFIG register */
 
 /* TILER_CONFIG register */