reg = <0x0 0xff63e000 0x0 0x48>;
};
- aml_tdes {
- compatible = "amlogic,des_dma,tdes_dma";
- dev_name = "aml_tdes_dma";
- status = "okay";
- interrupts = <0 180 1 0 181 1>;
- reg = <0x0 0xff63e000 0x0 0x48>;
- };
-
aml_sha {
compatible = "amlogic,sha_dma";
dev_name = "aml_sha_dma";
struct dma_dsc *dsc = dd->descriptor;
uint32_t key_iv[12];
uint32_t *piv = key_iv + 8;
- uint32_t len = keylen;
+ int32_t len = keylen;
dma_addr_t dma_addr_key;
memset(key_iv, 0, sizeof(key_iv));
dma_addr_key = dma_map_single(dd->dev, key_iv,
sizeof(key_iv), DMA_TO_DEVICE);
- dsc->src_addr = (uint32_t)dma_addr_key;
- dsc->tgt_addr = 0;
- dsc->dsc_cfg.d32 = 0;
- dsc->dsc_cfg.b.length = len;
- dsc->dsc_cfg.b.mode = MODE_KEY;
- dsc->dsc_cfg.b.eoc = 1;
- dsc->dsc_cfg.b.owner = 1;
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_AXG)) {
+ uint32_t i = 0;
+ while (len > 0) {
+ dsc[i].src_addr = (uint32_t)dma_addr_key + i * 16;
+ dsc[i].tgt_addr = i * 16;
+ dsc[i].dsc_cfg.d32 = 0;
+ dsc[i].dsc_cfg.b.length = len > 16 ? 16 : len;
+ dsc[i].dsc_cfg.b.mode = MODE_KEY;
+ dsc[i].dsc_cfg.b.eoc = 0;
+ dsc[i].dsc_cfg.b.owner = 1;
+ i++;
+ len -= 16;
+ }
+ dsc[i - 1].dsc_cfg.b.eoc = 1;
+ } else {
+ dsc->src_addr = (uint32_t)dma_addr_key;
+ dsc->tgt_addr = 0;
+ dsc->dsc_cfg.d32 = 0;
+ dsc->dsc_cfg.b.length = len;
+ dsc->dsc_cfg.b.mode = MODE_KEY;
+ dsc->dsc_cfg.b.eoc = 1;
+ dsc->dsc_cfg.b.owner = 1;
+ }
dma_sync_single_for_device(dd->dev, dd->dma_descript_tab,
PAGE_SIZE, DMA_TO_DEVICE);
dma_ctx = dma_map_single(dd->dev, tctx->state,
sizeof(tctx->state), DMA_TO_DEVICE);
- dsc->src_addr = (uint32_t)dma_ctx;
- dsc->tgt_addr = 0;
- dsc->dsc_cfg.d32 = 0;
- dsc->dsc_cfg.b.length = sizeof(tctx->state);
- dsc->dsc_cfg.b.mode = MODE_KEY;
- dsc->dsc_cfg.b.eoc = 1;
- dsc->dsc_cfg.b.owner = 1;
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_AXG)) {
+ uint32_t i = 0;
+ int32_t len = sizeof(tctx->state);
+ while (len > 0) {
+ dsc[i].src_addr = (uint32_t)dma_ctx + i * 16;
+ dsc[i].tgt_addr = i * 16;
+ dsc[i].dsc_cfg.d32 = 0;
+ dsc[i].dsc_cfg.b.length = len > 16 ? 16 : len;
+ dsc[i].dsc_cfg.b.mode = MODE_KEY;
+ dsc[i].dsc_cfg.b.eoc = 0;
+ dsc[i].dsc_cfg.b.owner = 1;
+ i++;
+ len -= 16;
+ }
+ dsc[i - 1].dsc_cfg.b.eoc = 1;
+ } else {
+ dsc->src_addr = (uint32_t)dma_ctx;
+ dsc->tgt_addr = 0;
+ dsc->dsc_cfg.d32 = 0;
+ dsc->dsc_cfg.b.length = sizeof(tctx->state);
+ dsc->dsc_cfg.b.mode = MODE_KEY;
+ dsc->dsc_cfg.b.eoc = 1;
+ dsc->dsc_cfg.b.owner = 1;
+ }
ctx->dma_descript_tab = dma_map_single(dd->dev, ctx->descriptor,
PAGE_SIZE, DMA_TO_DEVICE);
dma_ctx = dma_map_single(dd->dev, tctx->state,
sizeof(tctx->state), DMA_TO_DEVICE);
- dsc->src_addr = (uint32_t)dma_ctx;
- dsc->tgt_addr = 0;
- dsc->dsc_cfg.d32 = 0;
- dsc->dsc_cfg.b.length = sizeof(tctx->state);
- dsc->dsc_cfg.b.mode = MODE_KEY;
- dsc->dsc_cfg.b.eoc = 1;
- dsc->dsc_cfg.b.owner = 1;
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_AXG)) {
+ uint32_t i = 0;
+ int32_t len = sizeof(tctx->state);
+ while (len > 0) {
+ dsc[i].src_addr = (uint32_t)dma_ctx + i * 16;
+ dsc[i].tgt_addr = i * 16;
+ dsc[i].dsc_cfg.d32 = 0;
+ dsc[i].dsc_cfg.b.length = len > 16 ? 16 : len;
+ dsc[i].dsc_cfg.b.mode = MODE_KEY;
+ dsc[i].dsc_cfg.b.eoc = 0;
+ dsc[i].dsc_cfg.b.owner = 1;
+ i++;
+ len -= 16;
+ }
+ dsc[i - 1].dsc_cfg.b.eoc = 1;
+ } else {
+ dsc->src_addr = (uint32_t)dma_ctx;
+ dsc->tgt_addr = 0;
+ dsc->dsc_cfg.d32 = 0;
+ dsc->dsc_cfg.b.length = sizeof(tctx->state);
+ dsc->dsc_cfg.b.mode = MODE_KEY;
+ dsc->dsc_cfg.b.eoc = 1;
+ dsc->dsc_cfg.b.owner = 1;
+ }
ctx->dma_descript_tab = dma_map_single(dd->dev, ctx->descriptor,
PAGE_SIZE, DMA_TO_DEVICE);
dma_addr_key = dma_map_single(dd->dev, key_iv,
sizeof(key_iv), DMA_TO_DEVICE);
- dsc->src_addr = (uintptr_t)dma_addr_key;
- dsc->tgt_addr = 0;
- dsc->dsc_cfg.d32 = 0;
- dsc->dsc_cfg.b.length = len;
- dsc->dsc_cfg.b.mode = MODE_KEY;
- dsc->dsc_cfg.b.eoc = 1;
- dsc->dsc_cfg.b.owner = 1;
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_AXG)) {
+ uint32_t i = 0;
+ while (len > 0) {
+ dsc[i].src_addr = (uint32_t)dma_addr_key + i * 16;
+ dsc[i].tgt_addr = i * 16;
+ dsc[i].dsc_cfg.d32 = 0;
+ dsc[i].dsc_cfg.b.length = len > 16 ? 16 : len;
+ dsc[i].dsc_cfg.b.mode = MODE_KEY;
+ dsc[i].dsc_cfg.b.eoc = 0;
+ dsc[i].dsc_cfg.b.owner = 1;
+ i++;
+ len -= 16;
+ }
+ dsc[i - 1].dsc_cfg.b.eoc = 1;
+ } else {
+ dsc->src_addr = (uintptr_t)dma_addr_key;
+ dsc->tgt_addr = 0;
+ dsc->dsc_cfg.d32 = 0;
+ dsc->dsc_cfg.b.length = len;
+ dsc->dsc_cfg.b.mode = MODE_KEY;
+ dsc->dsc_cfg.b.eoc = 1;
+ dsc->dsc_cfg.b.owner = 1;
+ }
dma_sync_single_for_device(dd->dev, dd->dma_descript_tab,
PAGE_SIZE, DMA_TO_DEVICE);
static void aml_tdes_unregister_algs(struct aml_tdes_dev *dd)
{
- int i;
+ int i = 0;
+
+ /*
+ * AXG and beyond does not support DES
+ * and thus we start from 2
+ */
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_AXG))
+ i = 2;
- for (i = 0; i < ARRAY_SIZE(tdes_algs); i++)
+ for (; i < ARRAY_SIZE(tdes_algs); i++)
crypto_unregister_alg(&tdes_algs[i]);
}
static int aml_tdes_register_algs(struct aml_tdes_dev *dd)
{
- int err, i, j;
+ int err = 0, i = 0, j = 0;
+
+ /*
+ * AXG and beyond does not support DES
+ * and thus we start from 2
+ */
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_AXG))
+ i = 2;
- for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) {
+ for (; i < ARRAY_SIZE(tdes_algs); i++) {
err = crypto_register_alg(&tdes_algs[i]);
if (err)
goto err_tdes_algs;