armv8: ls2080: Add SFP Configs for LS2080

In LS2080, SFP has version 3.4. It is in little endian. The base
address is 0x01e80200. SFP is used in Secure Boot to read fuses.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index bfaece2..35d5908 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@
 /* SMMU Defintions */
 #define SMMU_BASE                      0x05000000 /* GR0 Base */
 
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE                    0x04000000
 #define CCI_MN_RNF_NODEID_LIST         0x180

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 081519a..6f1b144 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@
 #define AHCI_BASE_ADDR1                                (CONFIG_SYS_IMMR + 0x02200000)
 #define AHCI_BASE_ADDR2                                (CONFIG_SYS_IMMR + 0x02210000)
 
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR            (CONFIG_SYS_IMMR + 0x00e80200)
+
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)

diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644 (file)
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@
 /* Number of SRKH registers */
 #define NUM_SRKH_REGS  8
 
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#if    defined(CONFIG_SYS_FSL_SFP_VER_3_2) ||  \
+       defined(CONFIG_SYS_FSL_SFP_VER_3_4)
 struct ccsr_sfp_regs {
        u32 ospr;               /* 0x200 */
        u32 ospr1;              /* 0x204 */