Summary: This patch adds command line option for enabling power10-vector support.
Reviewers: hfinkel, nemanjai, lei, amyk, #powerpc
Reviewed By: lei, amyk, #powerpc
Subscribers: wuzish, kbarton, hiraditya, shchenz, cfe-commits, llvm-commits
Tags: #llvm, #clang, #powerpc
Differential Revision: https://reviews.llvm.org/D80758
Group<m_ppc_Features_Group>;
def mno_power9_vector : Flag<["-"], "mno-power9-vector">,
Group<m_ppc_Features_Group>;
+def mpower10_vector : Flag<["-"], "mpower10-vector">,
+ Group<m_ppc_Features_Group>;
+def mno_power10_vector : Flag<["-"], "mno-power10-vector">,
+ Group<m_ppc_Features_Group>;
def mpower8_crypto : Flag<["-"], "mcrypto">,
Group<m_ppc_Features_Group>;
def mnopower8_crypto : Flag<["-"], "mno-crypto">,
HasFloat128 = true;
} else if (Feature == "+power9-vector") {
HasP9Vector = true;
+ } else if (Feature == "+power10-vector") {
+ HasP10Vector = true;
} else if (Feature == "+pcrelative-memops") {
HasPCRelativeMemops = true;
} else if (Feature == "+spe") {
Builder.defineMacro("__FLOAT128__");
if (HasP9Vector)
Builder.defineMacro("__POWER9_VECTOR__");
+ if (HasP10Vector)
+ Builder.defineMacro("__POWER10_VECTOR__");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
// - direct-move
// - float128
// - power9-vector
+// - power10-vector
// then go ahead and error since the customer has expressed an incompatible
// set of options.
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
Found |= FindVSXSubfeature("+float128", "-mfloat128");
Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
+ Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
// Return false if any vsx subfeatures was found.
return !Found;
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap<bool> &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
return;
}
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
.Default(false);
.Case("direct-move", true)
.Case("power8-vector", true)
.Case("power9-vector", true)
+ .Case("power10-vector", true)
.Case("float128", true)
.Default(false);
if (FeatureHasVSX)
Features["vsx"] = Features["altivec"] = true;
if (Name == "power9-vector")
Features["power8-vector"] = true;
+ else if (Name == "power10-vector")
+ Features["power8-vector"] = Features["power9-vector"] = true;
if (Name == "pcrel")
Features["pcrelative-memops"] = true;
else
// features.
if ((Name == "altivec") || (Name == "vsx"))
Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
- Features["float128"] = Features["power9-vector"] = false;
+ Features["float128"] = Features["power9-vector"] =
+ Features["power10-vector"] = false;
if (Name == "power8-vector")
- Features["power9-vector"] = false;
+ Features["power9-vector"] = Features["power10-vector"] = false;
+ else if (Name == "power9-vector")
+ Features["power10-vector"] = false;
if (Name == "pcrel")
Features["pcrelative-memops"] = false;
else
bool HasExtDiv = false;
bool HasP9Vector = false;
bool HasSPE = false;
+ bool HasP10Vector = false;
bool HasPCRelativeMemops = false;
protected:
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 %s 2>&1 | FileCheck %s \
+// RUN: -check-prefix=CHECK-DEFAULT-P10
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
static_assert(false, "P9V enabled");
#endif
+#ifdef __POWER10_VECTOR__
+static_assert(false, "P10V enabled");
+#endif
+
#if !defined(__VSX__) && !defined(__POWER8_VECTOR__) && \
!defined(__POWER9_VECTOR__)
static_assert(false, "Neither enabled");
// CHECK-DEFAULT: VSX enabled
// CHECK-DEFAULT: P8V enabled
// CHECK-DEFAULT-P9: P9V enabled
+// CHECK-DEFAULT-P10: P10V enabled
// CHECK-NVSX-P8V: error: option '-mpower8-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX-P9V: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-P10V: error: option '-mpower10-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power8-vector -mpower8-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P8VECTOR %s
// CHECK-P8VECTOR: "-target-feature" "+power8-vector"
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOP10VECTOR %s
+// CHECK-NOP10VECTOR: "-target-feature" "-power10-vector"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-power10-vector -mpower10-vector -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-P10VECTOR %s
+// CHECK-P10VECTOR: "-target-feature" "+power10-vector"
+
// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-crbits -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
// CHECK-NOCRBITS: "-target-feature" "-crbits"
"Enable POWER9 vector instructions",
[FeatureISA3_0, FeatureP8Vector,
FeatureP9Altivec]>;
+def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector",
+ "true",
+ "Enable POWER10 vector instructions",
+ [FeatureISA3_1, FeatureP9Vector]>;
// A separate feature for this even though it is equivalent to P9Vector
// because this is a feature of the implementation rather than the architecture
// and may go away with future CPU's.
// still exist with the exception of those we know are Power9 specific.
list<SubtargetFeature> P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector];
list<SubtargetFeature> P10SpecificFeatures = [];
list<SubtargetFeature> P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
+ HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;
HasFCPSGN = false;
bool HasP8Crypto;
bool HasP9Vector;
bool HasP9Altivec;
+ bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
bool HasFCPSGN;
bool hasP8Crypto() const { return HasP8Crypto; }
bool hasP9Vector() const { return HasP9Vector; }
bool hasP9Altivec() const { return HasP9Altivec; }
+ bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }