bool "Support kmp204x"
select VENDOR_KM
+config TARGET_KMCENT2
+ bool "Support kmcent2"
+ select VENDOR_KM
+
config TARGET_XPEDITE520X
bool "Support xpedite520x"
select ARCH_MPC8548
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb
dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2021 Niel Fourie <lusus@denx.de>
+ */
+
+#include <config.h>
+
+/ {
+
+ aliases {
+ spi0 = "/soc@ffe000000/spi@110000";
+ i2c0 = "/soc@ffe000000/i2c@118000";
+ i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0";
+ i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1";
+ i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7";
+ i2c4 = "/soc@ffe000000/i2c@118100";
+ /delete-property/ pci1;
+ /delete-property/ pci2;
+ /delete-property/ pci3;
+ };
+
+ chosen {
+ stdout-path = "/soc@ffe000000/serial@11c500";
+ };
+
+ soc@ffe000000 {
+ u-boot,dm-pre-reloc;
+ spi@110000 {
+ /* This documents where km_fpgacfg should be appear */
+ fpga@0 {
+ compatible = "keymile,fpga-conf";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ sdhc@114000 {
+ status = "okay";
+ };
+
+ i2c@118000 {
+ u-boot,dm-pre-reloc;
+ mux@70 {
+ i2c@1 { /* IVM bus */
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ serial@11c500 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <200000000>;
+ };
+
+ fman@400000 {
+ ethernet@e0000 {
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e8000 {
+ phy-connection-type = "rgmii-id";
+ };
+ };
+
+ };
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t104x";
+ law_trgt_if = <0>;
+ };
+
+ binman {
+ filename = "u-boot-with-dtb.bin";
+ skip-at-start = <CONFIG_SYS_TEXT_BASE>;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = <CONFIG_SYS_MONITOR_LEN>;
+
+ u-boot-with-ucode-ptr {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ optional-ucode;
+ };
+
+ u-boot-dtb-with-ucode {
+ align = <256>;
+ };
+ powerpc-mpc85xx-bootpg-resetvec {
+ offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+ };
+ };
+};
Page size of inventory in EEPROM.
source "board/keymile/km83xx/Kconfig"
+source "board/keymile/kmcent2/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
}
+ if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) {
+ /* 3rd ethernet interface */
+ process_mac(valbuf, page2, 2, true);
+ env_set((char *)"eth4addr", (char *)valbuf);
+ }
return 0;
}
--- /dev/null
+if TARGET_KMCENT2
+
+config SYS_BOARD
+ default "kmcent2"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmcent2"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_T1040
+ select PHYS_64BIT
+
+endif
--- /dev/null
+KMCENT2 BOARD
+M: Niel Fourie <lusus@denx.de>
+S: Maintained
+F: board/keymile/kmcent2/
+F: include/configs/kmcent2.h
+F: configs/kmcent2_defconfig
+F: arch/powerpc/dts/kmcent2.dts
+F: arch/powerpc/dts/kmcent2-u-boot.dtsi
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Keymile AG
+# Rainer Boschung <rainer.boschung@keymile.com>
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+
+obj-y += kmcent2.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += ../common/common.o
+obj-y += ../common/ivm.o
+obj-y += ../common/qrio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+#include <asm/mpc85xx_gpio.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
+#define DQSn_START(n, start) ((start) << DQSn_POS(n))
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+
+ /* 1/2 clk delay between wr command and data strobe */
+ popts->write_data_delay = 4;
+ /* clk lauched 1/2 applied cylcle after address command */
+ popts->clk_adjust = 4;
+ /* 1T timing: command/address held for only 1 cycle */
+ popts->twot_en = 0;
+ popts->threet_en = 0;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x3b;
+
+ /* we have only one module, half str should be OK */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ /* set for DDR3-1600 */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x7;
+ /* DQS write leveling start time according layout */
+ popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
+ DQSn_START(2, 0x06) |
+ DQSn_START(3, 0x07) |
+ DQSn_START(4, 0x07));
+ popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
+ DQSn_START(6, 0x08) |
+ DQSn_START(7, 0x08) |
+ DQSn_START(8, 0x08));
+
+ /*
+ * rtt and wtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+int dram_init(void)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/cache.h>
+#include <asm/fsl_fdt.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <net.h>
+#include <netdev.h>
+#include <vsc9953.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+ printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
+
+ return 0;
+}
+
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* board specific IFC configuration: increased bus turnaround time */
+ setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
+
+ /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
+ setbits_be32(&gur->ddrclkdr, 0x40000000);
+
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
+ /* configure PRST lines for the application: */
+ /*
+ * ETHSW_DDR_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_ETHSW_DDR_RST, true);
+ /*
+ * XES_PHY_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_XES_PHY_RST, true);
+ /*
+ * ES_PHY_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_ES_PHY_RST, true);
+ /*
+ * EFE_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_EFE_RST, true);
+ /*
+ * BFTIC4_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_BFTIC4_RST, true);
+ /*
+ * DPAXE_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_DPAXE_RST, true);
+ /*
+ * PEXSW_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_PEXSW_RST, false, false);
+ /*
+ * PEXSW_NT_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_PEXSW_NT_RST, false, false);
+ /*
+ * BOBCAT_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_BOBCAT_RST, false, false);
+ /*
+ * FEMT_RST:
+ * reset at power-up and unit reset only and enable WD
+ */
+ qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_FEMT_RST, true);
+ /*
+ * FOAM_RST:
+ * reset at power-up and unit reset only and enable WD
+ */
+ qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_FOAM_RST, true);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ int ret = 0;
+
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+ setup_qbman_portals();
+
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
+ return ret;
+}
+
+unsigned long get_serial_clock(unsigned long dummy)
+{
+ return (gd->bus_clk / 2);
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+ return 66666666;
+}
+
+int misc_init_f(void)
+{
+ /* configure QRIO pis for i2c deblocking */
+ i2c_deblock_gpio_cfg();
+
+ /*
+ * CFE_RST (front phy):
+ * reset at power-up, unit and core reset, deasset reset w/o WD
+ */
+ qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(KM_CFE_RST, false, false);
+
+ /*
+ * ZL30158_RST (PTP clock generator):
+ * reset at power-up only, deassert reset and enable WD on it
+ */
+ qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
+ qrio_prst(KM_ZL30158_RST, false, false);
+
+ /*
+ * ZL30364_RST (EEC generator):
+ * reset at power-up only, deassert reset and enable WD on it
+ */
+ qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
+ qrio_prst(KM_ZL30364_RST, false, false);
+
+ return 0;
+}
+
+#define USED_SRDS_BANK 0
+#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
+
+#define BRG01_IOCLK12 0x02000000
+#define EC2_GTX_CLK125 0x08000000
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
+ ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* check SERDES bank 0 reference clock */
+ u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0);
+
+ if (actual & SRDS_PLLCR0_POFF)
+ printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
+ if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
+ printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
+ USED_SRDS_BANK,
+ serdes_clock_to_string(EXPECTED_SRDS_RFCK),
+ serdes_clock_to_string(actual));
+ }
+
+ /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
+ out_be32(&scfg->qeioclkcr,
+ in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
+
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+ /* Fix polarity of Card Detect and Write Protect */
+ out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
+
+ /*
+ * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
+ * to EC2
+ */
+ out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
+
+ return 0;
+}
+
+int hush_init_var(void)
+{
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ const char *kmem;
+ /* DIP switch support on BFTIC */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)SYS_BFTIC_BASE;
+ u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ env_set("actual_bank", "0");
+ }
+
+ set_km_env();
+
+ /*
+ * bootm_size is used to fixup the FDT memory node
+ * set it to kernelmem that has the same value
+ */
+ kmem = env_get("kernelmem");
+ if (kmem)
+ env_set("bootm_size", kmem);
+
+ return 0;
+}
+
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+ int node, ret;
+ char path[24];
+ unsigned char mac_addr[6];
+
+ /*
+ * Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
+ * get the mac addr from env
+ */
+ if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
+ printf("eth4addr env variable not defined\n");
+ return;
+ }
+
+ /* local management port */
+ strcpy(path, "/soc/fman/ethernet@e8000");
+ node = fdt_path_offset(blob, path);
+ if (node < 0) {
+ printf("no %s\n", path);
+ return;
+ }
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("%s\n\terror setting local-mac-address property\n",
+ path);
+ }
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = env_get_bootm_low();
+ size = env_get_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_liodn(blob);
+
+ fdt_fixup_fman_mac_addresses(blob);
+
+ if (hwconfig("qe-tdm"))
+ fdt_del_diu(blob);
+ return 0;
+}
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT QRIO_GPIO_A
+#define SELFTEST_PIN 0
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+#include <asm/fsl_law.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
+/* other application LAW are not used in u-boot */
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+ 0, 2, BOOKE_PAGESZ_128M, 1),
+
+ /* *I*G* - PCI1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI1 I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+ /* QRIO */
+ SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 11, BOOKE_PAGESZ_64K, 1),
+ /* MRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 12, BOOKE_PAGESZ_128M, 1),
+ /* BFTIC */
+ SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 13, BOOKE_PAGESZ_128M, 1),
+ /*
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so do not use them here!!.
+ */
+ /* PAXE */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+ MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 16, BOOKE_PAGESZ_128M, 1)
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xebf40000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_KM_IVM_BUS=2
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
+CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
+CONFIG_MPC85xx=y
+CONFIG_TARGET_KMCENT2=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND_TRIMFFS=y
+# CONFIG_CMD_SATA is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
+CONFIG_MP=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=ffa000000.flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),128k(zarlink),512k(res),62m(ubi0),128k(envred),128k(env),768k(u-boot);ffa000000.flash:-(ubi1);"
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_ADDR=0xebf20000
+CONFIG_ENV_ADDR_REDUND=0xebf00000
+CONFIG_DM=y
+# CONFIG_FSL_SATA is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_FSL_CAAM=y
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_FMAN_ENET=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_FSL_ESPI=y
+CONFIG_WATCHDOG=y
+CONFIG_FS_CRAMFS=y
+CONFIG_BCH=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZO=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ */
+
+#ifndef __KMCENT2_H
+#define __KMCENT2_H
+
+#define CONFIG_HOSTNAME "kmcent2"
+#define KM_BOARD_NAME CONFIG_HOSTNAME
+
+/*
+ * The Linux fsl_fman driver needs to be able to process frames with more
+ * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
+ * parameters
+ */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
+
+#include "km/keymile-common.h"
+
+/* Application IFC chip selects */
+#define SYS_LAWAPP_BASE 0xc0000000
+#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
+
+/* Application IFC CS4 MRAM */
+#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
+#define SYS_MRAM_CSPR_EXT (0x0f)
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+ CSPR_PORT_SIZE_8 | /* 8 bit */ \
+ CSPR_MSEL_GPCM | /* msel = gpcm */ \
+ CSPR_V /* bank is valid */)
+#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
+#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
+/* MRAM Timing parameters for IFC CS4 */
+#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0xe))
+#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \
+ FTIM2_GPCM_TCH(0x2) | \
+ FTIM2_GPCM_TWP(0x8))
+#define SYS_MRAM_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+
+/* Application IFC CS6: BFTIC */
+#define SYS_BFTIC_BASE 0xd0000000
+#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE)
+#define SYS_BFTIC_CSPR_EXT (0x0f)
+#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40
+/* BFTIC Timing parameters for IFC CS6 */
+#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_BFTIC_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+
+/* Application IFC CS7 PAXE */
+#define CONFIG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define SYS_PAXE_CSPR_EXT (0x0f)
+#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40
+/* PAXE Timing parameters for IFC CS7 */
+#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_PAXE_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+
+/* PRST */
+#define KM_BFTIC4_RST 0
+#define KM_DPAXE_RST 1
+#define KM_FEMT_RST 3
+#define KM_FOAM_RST 4
+#define KM_EFE_RST 5
+#define KM_ES_PHY_RST 6
+#define KM_XES_PHY_RST 7
+#define KM_ZL30158_RST 8
+#define KM_ZL30364_RST 9
+#define KM_BOBCAT_RST 10
+#define KM_ETHSW_DDR_RST 12
+#define KM_CFE_RST 13
+#define KM_PEXSW_RST 14
+#define KM_PEXSW_NT_RST 15
+
+/* QRIO GPIOs used for deblocking */
+#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
+#define KM_I2C_DEBLOCK_SCL 20
+#define KM_I2C_DEBLOCK_SDA 21
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+
+#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+/* Environment in parallel NOR-Flash */
+#define CONFIG_ENV_TOTAL_SIZE 0x040000
+#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+/* POST memory regions test */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE 256 << 10
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE 0x0
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR flash on IFC CS0 */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_NOR | /* MSEL = NOR */\
+ CSPR_V) /* valid */
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
+ CSOR_NOR_TRHZ_20 | \
+ CSOR_NOR_BCTLD)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x7) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x21) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x21))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \
+ FTIM2_NOR_TCS(0x1) | \
+ FTIM2_NOR_TWP(0xb) | \
+ FTIM2_NOR_TWPH(0x6))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* More NOR Flash params */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC CS1*/
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xfa000000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_NAND | /* MSEL = NAND */\
+ CSPR_V) /* valid */
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
+ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
+ CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
+ CSOR_NAND_PGS_2K | /* Page size = 2K */ \
+ CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \
+ CSOR_NAND_PB(64) | /* 64 Pages/Block */ \
+ CSOR_NAND_TRHZ_40 | /**/ \
+ CSOR_NAND_BCTLD) /**/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+ FTIM0_NAND_TWP(0x8) | \
+ FTIM0_NAND_TWCHT(0x3) | \
+ FTIM0_NAND_TWH(0x5))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+ FTIM1_NAND_TWBE(0x1e) | \
+ FTIM1_NAND_TRR(0x6) | \
+ FTIM1_NAND_TRP(0x8))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+ FTIM2_NAND_TREH(0x5) | \
+ FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* More NAND Flash Params */
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* QRIO on IFC CS2 */
+#define CONFIG_SYS_QRIO_BASE 0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define SYS_QRIO_CSPR_EXT (0x0f)
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\
+ CSOR_GPCM_BCTLD)
+/* QRIO Timing parameters for IFC CS2 */
+#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x6))
+#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x7))
+#define SYS_QRIO_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+
+#define CONFIG_MISC_INIT_F
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
+
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/*
+ * Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ * Retain non-DM serial port for debug purposes.
+ */
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#endif
+
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
+#define CONFIG_SYS_QE_FW_ADDR 0xE8040000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+/* Qman / Bman */
+/* RGMII (FM1@DTESC5) is local managemant interface */
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
+#define CONFIG_ETHPRIME "fm1-mac5"
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
+#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV
+#endif
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize}\0" \
+ "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
+ "set_fdthigh=true\0" \
+ "checkfdt=true\0" \
+ "fpgacfg=true\0" \
+ ""
+
+#define CONFIG_HW_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=protect off " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "erase " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "protect on " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ CONFIG_KM_NEW_ENV \
+ CONFIG_HW_ENV_SETTINGS \
+ "EEprom_ivm=pca9547:70:9\0" \
+ ""
+
+#endif /* __KMCENT2_H */
projects / platform / kernel / u-boot.git / commitdiff