staging: rtl8192e: Remove unused variable rfHSSIPara1 and rfSwitchControl
authorPhilipp Hortmann <philipp.g.hortmann@gmail.com>
Sat, 11 Mar 2023 21:51:49 +0000 (22:51 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 16 Mar 2023 08:37:01 +0000 (09:37 +0100)
Remove unused variable rfHSSIPara1 and rfSwitchControl because they are
just once set and not used. Remove unused constants as well.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Reviewed-by: Dan Carpenter <error27@gmail.com>
Link: https://lore.kernel.org/r/5f13420ce5598d447aaad0fe43b807467e0a15bb.1678569965.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/staging/rtl8192e/rtl8192e/r8190P_def.h
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h

index 2236c1a..d42eac4 100644 (file)
@@ -106,9 +106,7 @@ struct bb_reg_definition {
        u32 rfintfo;
        u32 rfintfe;
        u32 rf3wireOffset;
-       u32 rfHSSIPara1;
        u32 rfHSSIPara2;
-       u32 rfSwitchControl;
        u32 rfAGCControl1;
        u32 rfAGCControl2;
        u32 rfRxIQImbalance;
index 87f2871..add3de1 100644 (file)
@@ -368,21 +368,11 @@ static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev)
        priv->phy_reg_def[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
        priv->phy_reg_def[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 
-       priv->phy_reg_def[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
-       priv->phy_reg_def[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
-       priv->phy_reg_def[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
-       priv->phy_reg_def[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
-
        priv->phy_reg_def[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
        priv->phy_reg_def[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
        priv->phy_reg_def[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
        priv->phy_reg_def[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 
-       priv->phy_reg_def[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
-       priv->phy_reg_def[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
-       priv->phy_reg_def[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
-       priv->phy_reg_def[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
-
        priv->phy_reg_def[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
        priv->phy_reg_def[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
        priv->phy_reg_def[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
index b68e84d..5062be5 100644 (file)
 #define rFPGA0_TxGainStage             0x80c
 #define rFPGA0_RFTiming1               0x810
 #define rFPGA0_RFTiming2               0x814
-#define rFPGA0_XA_HSSIParameter1       0x820
 #define rFPGA0_XA_HSSIParameter2       0x824
-#define rFPGA0_XB_HSSIParameter1       0x828
 #define rFPGA0_XB_HSSIParameter2       0x82c
-#define rFPGA0_XC_HSSIParameter1       0x830
 #define rFPGA0_XC_HSSIParameter2       0x834
-#define rFPGA0_XD_HSSIParameter1       0x838
 #define rFPGA0_XD_HSSIParameter2       0x83c
 #define rFPGA0_XA_LSSIParameter                0x840
 #define rFPGA0_XB_LSSIParameter                0x844
 #define rFPGA0_RFWakeUpParameter       0x850
 #define rFPGA0_RFSleepUpParameter      0x854
-#define rFPGA0_XAB_SwitchControl       0x858
-#define rFPGA0_XCD_SwitchControl       0x85c
 #define rFPGA0_XA_RFInterfaceOE                0x860
 #define rFPGA0_XB_RFInterfaceOE                0x864
 #define rFPGA0_XAB_RFInterfaceSW       0x870