exynos4210-trats.dtb \
exynos5250-smdk5250.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
+ integratorcp.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-dns325.dtb \
compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC";
- interrupt-parent = <&intc>;
-
- intc: interrupt-controller {
- compatible = "marvell,orion-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0xf1020204 0x04>,
- <0xf1020214 0x04>;
- };
-
- mbus@f1000000 {
+ soc@f1000000 {
compatible = "simple-bus";
- ranges = <0 0xf1000000 0x4000000>;
#address-cells = <1>;
#size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
+ 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
+ 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
+ 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
+ 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
+ 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
+ 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
+ 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
+
+ l2: l2-cache {
+ compatible = "marvell,tauros2-cache";
+ marvell,tauros2-cache-features = <0>;
+ };
+
+ intc: interrupt-controller {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x20204 0x04>, <0x20214 0x04>;
+ };
uart0: serial@12000 {
compatible = "ns16550a";
status = "disabled";
};
- wdt: wdt@20300 {
- compatible = "marvell,orion-wdt";
- reg = <0x20300 0x28>;
- };
-
gpio0: gpio@d0400 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
nr-ports = <1>;
status = "disabled";
};
+
+ crypto: crypto@30000 {
+ compatible = "marvell,orion-crypto";
+ reg = <0x30000 0x10000>,
+ <0xc8000000 0x800>;
+ reg-names = "regs", "sram";
+ interrupts = <31>;
+ status = "okay";
+ };
};
};
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+ >;
+ };
+ };
+
+ arm2 {
+ pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
+ fsl,pins = <
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
>;
wp-gpios = <&gpio6 14 0>;
vmmc-supply = <®_3p3v>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
+ pinctrl-0 = <&pinctrl_usdhc3_1
+ &pinctrl_usdhc3_arm2>;
status = "okay";
};
#size-cells = <0>;
button@1 {
label = "Function Button";
- linux,code = <132>;
+ linux,code = <357>;
gpios = <&gpio1 9 1>;
};
button@2 {
label = "Power-on Switch";
- linux,code = <116>;
+ linux,code = <0>;
+ linux,input-type = <5>;
gpios = <&gpio1 10 1>;
};
button@3 {
label = "Power-auto Switch";
- linux,code = <142>;
+ linux,code = <1>;
+ linux,input-type = <5>;
gpios = <&gpio1 11 1>;
};
};
compatible = "gpio-leds";
led@1 {
- label = "lschlv2:blue:func";
+ label = "lsxl:blue:func";
gpios = <&gpio1 4 1>;
};
led@2 {
- label = "lschlv2:red:alarm";
+ label = "lsxl:red:alarm";
gpios = <&gpio1 5 1>;
};
led@3 {
- label = "lschlv2:amber:info";
+ label = "lsxl:amber:info";
gpios = <&gpio1 6 1>;
};
led@4 {
- label = "lschlv2:blue:power";
+ label = "lsxl:blue:power";
gpios = <&gpio1 7 1>;
linux,default-trigger = "default-on";
};
led@5 {
- label = "lschlv2:red:func";
+ label = "lsxl:red:func";
gpios = <&gpio1 16 1>;
};
};
ehci@d8007100 {
compatible = "via,vt8500-ehci";
reg = <0xd8007100 0x200>;
- interrupts = <43>;
+ interrupts = <1>;
};
uhci@d8007300 {
compatible = "platform-uhci";
reg = <0xd8007300 0x200>;
- interrupts = <43>;
+ interrupts = <0>;
};
fb@d8050800 {
#include <linux/irq.h>
#include <plat/time.h>
#include <linux/platform_data/usb-ehci-orion.h>
+#include <plat/irq.h>
#include <plat/common.h>
#include <plat/addr-map.h>
#include "common.h"
orion_clkdev_add(NULL, "orion-ehci.0", usb0);
orion_clkdev_add(NULL, "orion-ehci.1", usb1);
- orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
- orion_clkdev_add("0", "sata_mv.0", sata);
+ orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
+ orion_clkdev_add(NULL, "sata_mv.0", sata);
orion_clkdev_add("0", "pcie", pex0);
orion_clkdev_add("1", "pcie", pex1);
orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
(dove_tclk + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init();
+ tauros2_init(0);
#endif
dove_setup_cpu_mbus();
dove_ehci0_init();
dove_ehci1_init();
dove_pcie_init(1, 1);
- dove_crypto_init();
of_platform_populate(NULL, of_default_bus_match_table,
dove_auxdata_lookup, NULL);
#include <linux/kernel.h>
#include <linux/pci.h>
+#include <linux/clk.h>
#include <video/vga.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
if (orion_pcie_link_up(base)) {
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+ struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
+
+ if (!IS_ERR(clk))
+ clk_prepare_enable(clk);
printk(KERN_INFO "link up\n");
kirkwood_setup_cpu_mbus();
-#ifdef CONFIG_CACHE_FEROCEON_L2
kirkwood_l2_init();
-#endif
/* Setup root of clk tree */
kirkwood_clk_init();
void __init kirkwood_l2_init(void)
{
+#ifdef CONFIG_CACHE_FEROCEON_L2
#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
feroceon_l2_init(1);
writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
feroceon_l2_init(0);
#endif
+#endif
}
void __init kirkwood_init(void)
kirkwood_setup_cpu_mbus();
-#ifdef CONFIG_CACHE_FEROCEON_L2
kirkwood_l2_init();
-#endif
/* Setup root of clk tree */
kirkwood_clk_init();
CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
- CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
+ CLK("omap-gpmc", "fck", &dummy_ck, CK_443X),
CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
+ spin_lock_irqsave(&clkdm->lock, flags);
+
/*
* For arch's with no autodeps, clkcm_clk_enable
* should be called for every clock instance or hwmod that is
* enabled, so the clkdm can be force woken up.
*/
- if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
+ if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
return 0;
+ }
- spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
+ spin_lock_irqsave(&clkdm->lock, flags);
+
if (atomic_read(&clkdm->usecount) == 0) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
WARN_ON(1); /* underflow */
return -ERANGE;
}
- if (atomic_dec_return(&clkdm->usecount) > 0)
+ if (atomic_dec_return(&clkdm->usecount) > 0) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
return 0;
+ }
- spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
oh = omap_hwmod_lookup("dmic");
if (!oh) {
- printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+ pr_err("Could not look up dmic hw_mod\n");
return;
}
}
-static void __devinit gpmc_mem_init(void)
+static int __devinit gpmc_mem_init(void)
{
- int cs;
+ int cs, rc;
unsigned long boot_rom_space = 0;
/* never allocate the first page, to facilitate bug detection;
if (!gpmc_cs_mem_enabled(cs))
continue;
gpmc_cs_get_memconf(cs, &base, &size);
- if (gpmc_cs_insert_mem(cs, base, size) < 0)
- BUG();
+ rc = gpmc_cs_insert_mem(cs, base, size);
+ if (IS_ERR_VALUE(rc)) {
+ while (--cs >= 0)
+ if (gpmc_cs_mem_enabled(cs))
+ gpmc_cs_delete_mem(cs);
+ return rc;
+ }
}
+
+ return 0;
}
static __devinit int gpmc_probe(struct platform_device *pdev)
{
+ int rc;
u32 l;
struct resource *res;
dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
GPMC_REVISION_MINOR(l));
- gpmc_mem_init();
+ rc = gpmc_mem_init();
+ if (IS_ERR_VALUE(rc)) {
+ clk_disable_unprepare(gpmc_l3_clk);
+ clk_put(gpmc_l3_clk);
+ dev_err(gpmc_dev, "failed to reserve memory\n");
+ return rc;
+ }
if (IS_ERR_VALUE(gpmc_setup_irq()))
dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
- OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
+ OMAP44XX_LOCAL_TWD_BASE, 29);
#endif
static void __init omap4_timer_init(void)
CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
};
-static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
+static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
{
struct clk *clock_upll;
struct clk *clock_h;
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 32K*8way */
- l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
+ l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
#endif
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
#include <linux/clkdev.h>
#include <mach/common.h>
-#define FRQMR 0xffc80014
-#define MSTPCR0 0xffc80030
-#define MSTPCR1 0xffc80034
-#define MSTPCR3 0xffc8003c
-#define MSTPSR1 0xffc80044
-#define MSTPSR4 0xffc80048
-#define MSTPSR6 0xffc8004c
-#define MSTPCR4 0xffc80050
-#define MSTPCR5 0xffc80054
-#define MSTPCR6 0xffc80058
-#define MSTPCR7 0xffc80040
+#define FRQMR IOMEM(0xffc80014)
+#define MSTPCR0 IOMEM(0xffc80030)
+#define MSTPCR1 IOMEM(0xffc80034)
+#define MSTPCR3 IOMEM(0xffc8003c)
+#define MSTPSR1 IOMEM(0xffc80044)
+#define MSTPSR4 IOMEM(0xffc80048)
+#define MSTPSR6 IOMEM(0xffc8004c)
+#define MSTPCR4 IOMEM(0xffc80050)
+#define MSTPCR5 IOMEM(0xffc80054)
+#define MSTPCR6 IOMEM(0xffc80058)
+#define MSTPCR7 IOMEM(0xffc80040)
/* ioremap() through clock mapping mandatory to avoid
* collision with ARM coherent DMA virtual memory range.
.init_early = tegra20_init_early,
.init_irq = tegra_dt_init_irq,
.handle_irq = gic_handle_irq,
- .timer = &tegra_timer,
+ .timer = &tegra_sys_timer,
.init_machine = tegra_dt_init,
.init_late = tegra_dt_init_late,
.restart = tegra_assert_system_reset,
.init_early = tegra30_init_early,
.init_irq = tegra_dt_init_irq,
.handle_irq = gic_handle_irq,
- .timer = &tegra_timer,
+ .timer = &tegra_sys_timer,
.init_machine = tegra30_dt_init,
.init_late = tegra_init_late,
.restart = tegra_assert_system_reset,
void __init tegra_paz00_wifikill_init(void);
-extern struct sys_timer tegra_timer;
+extern struct sys_timer tegra_sys_timer;
#endif
static struct clk *tegra_list_clks[] = {
&tegra_apbdma,
&tegra_rtc,
+ &tegra_timer,
&tegra_i2s1,
&tegra_i2s2,
&tegra_spdif_out,
{
struct clk_tegra *c = to_clk_tegra(hw);
unsigned long input_rate = *prate;
- unsigned long output_rate = *prate;
+ u64 output_rate = *prate;
const struct clk_pll_freq_table *sel;
struct clk_pll_freq_table cfg;
int mul;
&tegra_apbdma,
&tegra_rtc,
&tegra_kbc,
+ &tegra_timer,
&tegra_kfuse,
&tegra_fuse,
&tegra_fuse_burn,
register_persistent_clock(NULL, tegra_read_persistent_clock);
}
-struct sys_timer tegra_timer = {
+struct sys_timer tegra_sys_timer = {
.init = tegra_init_timer,
};
#include <linux/smc91x.h>
#include <mach/hardware.h>
+#include "../mach-omap2/debug-devices.h"
/* Many OMAP development platforms reuse the same "debug board"; these
* platforms include H2, H3, H4, and Perseus2.
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
u &= ~(1 << pin);
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+ break;
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
u |= 1 << pin;
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+ break;
case IRQ_TYPE_EDGE_BOTH: {
u32 v;
else
u &= ~(1 << pin); /* rising */
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+ break;
}
}
return 0;
sharpsl_pcmcia_init_reset(skt);
}
-static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = {
+static struct pcmcia_low_level sharpsl_pcmcia_ops = {
.owner = THIS_MODULE,
.hw_init = sharpsl_pcmcia_hw_init,
.socket_state = sharpsl_pcmcia_socket_state,
SCp->buffers_residual, suffix);
}
+#ifdef CHECK_STRUCTURE
static void fas216_dumpinfo(FAS216_Info *info)
{
static int used = 0;
info->internal_done, info->magic_end);
}
-#ifdef CHECK_STRUCTURE
static void __fas216_checkmagic(FAS216_Info *info, const char *func)
{
int corruption = 0;
/*#define PSEUDO_DMA*/
#define OAKSCSI_PUBLIC_RELEASE 1
+#define DONT_USE_INTR
#define priv(host) ((struct NCR5380_hostdata *)(host)->hostdata)
#define NCR5380_local_declare() void __iomem *_base
struct s3c64xx_spi_dma_data {
unsigned ch;
- enum dma_data_direction direction;
+ enum dma_transfer_direction direction;
enum dma_ch dmach;
struct property *dma_prop;
};
if (tx) {
dma_data = &sdd->tx_dma;
- dma_data->direction = DMA_TO_DEVICE;
+ dma_data->direction = DMA_MEM_TO_DEV;
chan_str = "tx";
} else {
dma_data = &sdd->rx_dma;
- dma_data->direction = DMA_FROM_DEVICE;
+ dma_data->direction = DMA_DEV_TO_MEM;
chan_str = "rx";
}
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
};
-static void __init
+static void __devinit
ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
const struct mbus_dram_target_info *dram)
{
__do_kmalloc_node(size_t size, gfp_t gfp, int node, unsigned long caller)
{
unsigned int *m;
- int align = max(ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN);
+ int align = max_t(size_t, ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN);
void *ret;
gfp &= gfp_allowed_mask;
sp = virt_to_page(block);
if (PageSlab(sp)) {
- int align = max(ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN);
+ int align = max_t(size_t, ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN);
unsigned int *m = (unsigned int *)(block - align);
slob_free(m, *m + align);
} else
sp = virt_to_page(block);
if (PageSlab(sp)) {
- int align = max(ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN);
+ int align = max_t(size_t, ARCH_KMALLOC_MINALIGN, ARCH_SLAB_MINALIGN);
unsigned int *m = (unsigned int *)(block - align);
return SLOB_UNITS(*m) * SLOB_UNIT;
} else
projects / platform / kernel / linux-rpi.git / commitdiff