return;
}
+#ifdef __i386__
void mga_flush_write_combine(void)
{
int xchangeDummy;
" movl $0,%%eax ; cpuid ; pop %%edx ; pop %%ecx ; pop %%ebx ;"
" pop %%eax" : /* no outputs */ : /* no inputs */ );
}
+#endif
/* These are two age tags that will never be sent to
* the hardware */
}
}
+#ifdef __i386__
mga_flush_write_combine();
+#endif
atomic_inc(&dev_priv->pending_bufs);
MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL);
MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp);
* the status register will be correct
*/
+#ifdef __i386__
mga_flush_write_combine();
+#endif
MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL);
MGA_WRITE(MGAREG_PRIMEND, ((phys_head + num_dwords * 4) |
mga_dma_dispatch_clear(dev, clear.flags,
clear.clear_color, clear.clear_depth);
PRIMUPDATE(dev_priv);
+#ifdef __i386__
mga_flush_write_combine();
+#endif
mga_dma_schedule(dev, 1);
return 0;
}
PRIMUPDATE(dev_priv);
set_bit(MGA_BUF_SWAP_PENDING,
&dev_priv->current_prim->buffer_status);
+#ifdef __i386__
mga_flush_write_combine();
+#endif
mga_dma_schedule(dev, 1);
return 0;
}
AGEBUF(dev_priv, buf_priv);
buf_priv->discard = 1;
mga_freelist_put(dev, buf);
+#ifdef __i386__
mga_flush_write_combine();
+#endif
mga_dma_schedule(dev, 1);
return 0;
}
mga_dma_dispatch_vertex(dev, buf);
PRIMUPDATE(dev_priv);
+#ifdef __i386__
mga_flush_write_combine();
+#endif
mga_dma_schedule(dev, 1);
return 0;
}
mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
PRIMUPDATE(dev_priv);
+#ifdef __i386__
mga_flush_write_combine();
+#endif
mga_dma_schedule(dev, 1);
return 0;
}
return R128_READ(R128_CLOCK_CNTL_DATA);
}
+#ifdef __i386__
static void r128_flush_write_combine(void)
{
int xchangeDummy;
"pop %%ebx ;"
"pop %%eax" : /* no outputs */ : /* no inputs */ );
}
+#endif
static void r128_status(drm_device_t *dev)
{
dev_priv->ring_start,
write * sizeof(u32));
+#ifdef __i386__
/* Make sure WC cache has been flushed */
r128_flush_write_combine();
+#endif
dev_priv->sarea_priv->ring_write = write;
R128_WRITE(R128_PM4_BUFFER_DL_WPTR, write);
dev_priv->ring_start,
write * sizeof(u32));
+#ifdef __i386__
/* Make sure WC cache has been flushed */
r128_flush_write_combine();
+#endif
dev_priv->sarea_priv->ring_write = write;
R128_WRITE(R128_PM4_BUFFER_DL_WPTR, write);
r128_mark_vertbufs_done(dev);
}
+#ifdef __i386__
/* Make sure WC cache has been flushed (if in PIO mode) */
if (!dev_priv->cce_is_bm_mode) r128_flush_write_combine();
+#endif
/* FIXME: Add support for sending vertex buffer to the CCE here
instead of in client code. The v->prim holds the primitive