drm/i915/bxt: Determine PLL attached to pipe

Determine PLL attached to pipe (which is same as DDI PLL)

v2:
- rebased on upstream s/crtc_config/crtc_state/ (imre)

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c51565a..278f807 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9096,6 +9096,28 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
        return 0;
 }
 
+static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
+                               enum port port,
+                               struct intel_crtc_state *pipe_config)
+{
+       switch (port) {
+       case PORT_A:
+               pipe_config->ddi_pll_sel = SKL_DPLL0;
+               pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
+               break;
+       case PORT_B:
+               pipe_config->ddi_pll_sel = SKL_DPLL1;
+               pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
+               break;
+       case PORT_C:
+               pipe_config->ddi_pll_sel = SKL_DPLL2;
+               pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
+               break;
+       default:
+               DRM_ERROR("Incorrect port type\n");
+       }
+}
+
 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
                                enum port port,
                                struct intel_crtc_state *pipe_config)
@@ -9158,6 +9180,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
        if (IS_SKYLAKE(dev))
                skylake_get_ddi_pll(dev_priv, port, pipe_config);
+       else if (IS_BROXTON(dev))
+               bxt_get_ddi_pll(dev_priv, port, pipe_config);
        else
                haswell_get_ddi_pll(dev_priv, port, pipe_config);