2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+ * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add
+ __mips_loongson_ext.
+ (MIPS_ASE_LOONGSON_EXT_SPEC): New.
+ (BASE_DRIVER_SELF_SPECS): march=loongson3a implies
+ -mloongson-ext.
+ (ASM_SPEC): Add mloongson-ext and mno-loongson-ext.
+ * config/mips/mips.md (mul<mode>3, mul<mode>3_mul3_nohilo,
+ <u>div<mode>3, <u>mod<mode>3, prefetch): Use TARGET_LOONGSON_EXT
+ instead of TARGET_LOONGSON_3A.
+ * config/mips/mips.opt (-mloongson-ext): Add option.
+ * gcc/doc/invoke.texi (-mloongson-ext): Document.
+
+2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+
* config.gcc (extra_headers): Add loongson-mmiintrin.h.
* config/mips/loongson.md: Move to ...
* config/mips/loongson-mmi.md: here; Adjustment.
builtin_define ("__mips_loongson_mmi"); \
} \
\
+ /* Whether Loongson EXT modes are enabled. */ \
+ if (TARGET_LOONGSON_EXT) \
+ { \
+ builtin_define ("__mips_loongson_ext"); \
+ } \
+ \
/* Historical Octeon macro. */ \
if (TARGET_OCTEON) \
builtin_define ("__OCTEON__"); \
#define BASE_DRIVER_SELF_SPECS \
MIPS_ISA_NAN2008_SPEC, \
MIPS_ASE_DSP_SPEC, \
- MIPS_ASE_LOONGSON_MMI_SPEC
+ MIPS_ASE_LOONGSON_MMI_SPEC, \
+ MIPS_ASE_LOONGSON_EXT_SPEC
#define MIPS_ASE_DSP_SPEC \
"%{!mno-dsp: \
"%{!mno-loongson-mmi: \
%{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}"
+#define MIPS_ASE_LOONGSON_EXT_SPEC \
+ "%{!mno-loongson-ext: \
+ %{march=loongson3a: -mloongson-ext}}"
+
#define DRIVER_SELF_SPECS \
MIPS_ISA_LEVEL_SPEC, \
BASE_DRIVER_SELF_SPECS
%{mginv} %{mno-ginv} \
%{mmsa} %{mno-msa} \
%{mloongson-mmi} %{mno-loongson-mmi} \
+%{mloongson-ext} %{mno-loongson-ext} \
%{msmartmips} %{mno-smartmips} \
%{mmt} %{mno-mt} \
%{mfix-rm7000} %{mno-fix-rm7000} \
{
rtx lo;
- if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL)
+ if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL)
emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1],
operands[2]));
else if (ISA_HAS_<D>MUL3)
[(set (match_operand:GPR 0 "register_operand" "=d")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
- "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL"
+ "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL"
{
if (TARGET_LOONGSON_2EF)
return "<d>multu.g\t%0,%1,%2";
- else if (TARGET_LOONGSON_3A)
+ else if (TARGET_LOONGSON_EXT)
return "gs<d>multu\t%0,%1,%2";
else
return "<d>mul\t%0,%1,%2";
[(set (match_operand:GPR 0 "register_operand" "=&d")
(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
- "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV"
+ "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV"
{
if (TARGET_LOONGSON_2EF)
return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands);
- else if (TARGET_LOONGSON_3A)
+ else if (TARGET_LOONGSON_EXT)
return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands);
else
return mips_output_division ("<d>div<u>\t%0,%1,%2", operands);
[(set (match_operand:GPR 0 "register_operand" "=&d")
(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))]
- "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV"
+ "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV"
{
if (TARGET_LOONGSON_2EF)
return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands);
- else if (TARGET_LOONGSON_3A)
+ else if (TARGET_LOONGSON_EXT)
return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands);
else
return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands);
(match_operand 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
{
- if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
+ if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
{
/* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */
if (TARGET_64BIT)
mloongson-mmi
Target Report Mask(LOONGSON_MMI)
Use Loongson MultiMedia extensions Instructions (MMI) instructions.
+
+mloongson-ext
+Target Report Mask(LOONGSON_EXT)
+Use Loongson EXTension (EXT) instructions.
-mmicromips -mno-micromips @gol
-mmsa -mno-msa @gol
-mloongson-mmi -mno-loongson-mmi @gol
+-mloongson-ext -mno-loongson-ext @gol
-mfpu=@var{fpu-type} @gol
-msmartmips -mno-smartmips @gol
-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol
@opindex mno-loongson-mmi
Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI).
+@item -mloongson-ext
+@itemx -mno-loongson-ext
+@opindex mloongson-ext
+@opindex mno-loongson-ext
+Use (do not use) the MIPS Loongson EXTensions (EXT) instructions.
+
@item -mlong64
@opindex mlong64
Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+ * gcc.target/mips/mips.exp (mips_option_groups): Add
+ -mloongson-ext option.
+ (mips-dg-options): Add mips_option_dependency options
+ "-mmicromips" vs "-mno-loongson-ext",
+
+2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+
* gcc.target/mips/loongson-shift-count-truncated-1.c
(dg-options): Run under -mloongson-mmi option.
Include loongson-mmiintrin.h instead of loongson.h.
odd-spreg
msa
loongson-mmi
+ loongson-ext
} {
lappend mips_option_groups $option "-m(no-|)$option"
}
mips_option_dependency options "-mips16" "-mno-loongson-mmi"
mips_option_dependency options "-mmicromips" "-mno-loongson-mmi"
mips_option_dependency options "-msoft-float" "-mno-loongson-mmi"
+ mips_option_dependency options "-mmicromips" "-mno-loongson-ext"
# Work out information about the current ABI.
set abi_test_option_p [mips_test_option_p options abi]