drm/amdgpu: remove gfxhub ip
authorHuang Rui <ray.huang@amd.com>
Wed, 31 May 2017 15:46:26 +0000 (23:46 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 6 Jun 2017 20:59:03 +0000 (16:59 -0400)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/include/amd_shared.h

index 01ee69b..85dc464 100644 (file)
@@ -1862,7 +1862,6 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
        static enum amd_ip_block_type ip_order[] = {
                AMD_IP_BLOCK_TYPE_GMC,
                AMD_IP_BLOCK_TYPE_COMMON,
-               AMD_IP_BLOCK_TYPE_GFXHUB,
                AMD_IP_BLOCK_TYPE_MMHUB,
                AMD_IP_BLOCK_TYPE_IH,
        };
index 9198eb5..51efefe 100644 (file)
@@ -358,96 +358,3 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
        hub->vm_l2_pro_fault_cntl =
                SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 }
-
-static int gfxhub_v1_0_early_init(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_late_init(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_sw_init(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_sw_fini(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_hw_init(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_hw_fini(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_suspend(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_resume(void *handle)
-{
-       return 0;
-}
-
-static bool gfxhub_v1_0_is_idle(void *handle)
-{
-       return true;
-}
-
-static int gfxhub_v1_0_wait_for_idle(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_soft_reset(void *handle)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_set_clockgating_state(void *handle,
-                                         enum amd_clockgating_state state)
-{
-       return 0;
-}
-
-static int gfxhub_v1_0_set_powergating_state(void *handle,
-                                         enum amd_powergating_state state)
-{
-       return 0;
-}
-
-const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
-       .name = "gfxhub_v1_0",
-       .early_init = gfxhub_v1_0_early_init,
-       .late_init = gfxhub_v1_0_late_init,
-       .sw_init = gfxhub_v1_0_sw_init,
-       .sw_fini = gfxhub_v1_0_sw_fini,
-       .hw_init = gfxhub_v1_0_hw_init,
-       .hw_fini = gfxhub_v1_0_hw_fini,
-       .suspend = gfxhub_v1_0_suspend,
-       .resume = gfxhub_v1_0_resume,
-       .is_idle = gfxhub_v1_0_is_idle,
-       .wait_for_idle = gfxhub_v1_0_wait_for_idle,
-       .soft_reset = gfxhub_v1_0_soft_reset,
-       .set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
-       .set_powergating_state = gfxhub_v1_0_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
-{
-       .type = AMD_IP_BLOCK_TYPE_GFXHUB,
-       .major = 1,
-       .minor = 0,
-       .rev = 0,
-       .funcs = &gfxhub_v1_0_ip_funcs,
-};
index 69df356..baaa160 100644 (file)
@@ -484,7 +484,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_VEGA10:
                amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-               amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
@@ -501,7 +500,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                break;
        case CHIP_RAVEN:
                amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-               amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
index 0f58e95..0699031 100644 (file)
@@ -76,7 +76,6 @@ enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_UVD,
        AMD_IP_BLOCK_TYPE_VCE,
        AMD_IP_BLOCK_TYPE_ACP,
-       AMD_IP_BLOCK_TYPE_GFXHUB,
        AMD_IP_BLOCK_TYPE_MMHUB,
        AMD_IP_BLOCK_TYPE_VCN
 };