arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO
authorNicolas Frattaroli <frattaroli.nicolas@gmail.com>
Sat, 12 Nov 2022 16:04:01 +0000 (17:04 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 15 Nov 2022 10:46:15 +0000 (11:46 +0100)
This patch enables the PCIe2 on the CM4IO board when paired with
a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
enabled in this case to make the PHY work for this.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi

index e00568a..263ce40 100644 (file)
        };
 };
 
+/* phy for pcie */
+&combphy2 {
+       phy-supply = <&vcc3v3_sys>;
+       status = "okay";
+};
+
 &gmac1 {
        status = "okay";
 };
        status = "okay";
 };
 
+&pcie2x1 {
+       vpcie3v3-supply = <&vcc_3v3>;
+       status = "okay";
+};
+
 &rgmii_phy1 {
        status = "okay";
 };
index 1b97582..ce7165d 100644 (file)
        };
 };
 
+&pcie2x1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_reset_h>;
+       reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+
 &pinctrl {
        bt {
                bt_enable_h: bt-enable-h {
                };
        };
 
+       pcie {
+               pcie_clkreq_h: pcie-clkreq-h {
+                       rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+               pcie_reset_h: pcie-reset-h {
+                       rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;