enum nv_device_type type;
uint16_t device_id;
+ uint16_t chipset;
+
+ char device_name[64];
+ char chipset_name[16];
/* Populated if type == NV_DEVICE_TYPE_DIS */
struct {
uint8_t revision_id;
} pci;
+ uint8_t sm; /**< Shader model */
+
uint16_t cls_copy;
uint16_t cls_eng2d;
uint16_t cls_eng3d;
uint16_t cls_m2mf;
uint16_t cls_compute;
+
+ uint64_t vram_size_B;
};
#endif /* NV_DEVINFO_H */
pProperties->properties = (VkPhysicalDeviceProperties) {
.apiVersion = VK_MAKE_VERSION(1, 0, VK_HEADER_VERSION),
.driverVersion = vk_get_driver_version(),
- .vendorID = pdev->dev->vendor_id,
- .deviceID = pdev->dev->device_id,
+ .vendorID = NVIDIA_VENDOR_ID,
+ .deviceID = pdev->info.device_id,
.deviceType = pdev->info.type == NV_DEVICE_TYPE_DIS ?
VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU :
VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
.limits = (VkPhysicalDeviceLimits) {
.maxImageArrayLayers = 2048,
- .maxImageDimension1D = pdev->dev->chipset >= 0x130 ? 0x8000 : 0x4000,
- .maxImageDimension2D = pdev->dev->chipset >= 0x130 ? 0x8000 : 0x4000,
+ .maxImageDimension1D = pdev->info.chipset >= 0x130 ? 0x8000 : 0x4000,
+ .maxImageDimension2D = pdev->info.chipset >= 0x130 ? 0x8000 : 0x4000,
.maxImageDimension3D = 0x4000,
.maxImageDimensionCube = 0x8000,
.maxPushConstantsSize = NVK_MAX_PUSH_SIZE,
.maxMemoryAllocationCount = 1024,
- .bufferImageGranularity = pdev->dev->chipset >= 0x120 ? 0x400 : 0x10000,
- .maxFramebufferHeight = pdev->dev->chipset >= 0x130 ? 0x8000 : 0x4000,
- .maxFramebufferWidth = pdev->dev->chipset >= 0x130 ? 0x8000 : 0x4000,
+ .bufferImageGranularity = pdev->info.chipset >= 0x120 ? 0x400 : 0x10000,
+ .maxFramebufferHeight = pdev->info.chipset >= 0x130 ? 0x8000 : 0x4000,
+ .maxFramebufferWidth = pdev->info.chipset >= 0x130 ? 0x8000 : 0x4000,
.maxFramebufferLayers = 2048,
.maxColorAttachments = NVK_MAX_RTS,
.maxClipDistances = 8,
snprintf(pProperties->properties.deviceName,
sizeof(pProperties->properties.deviceName),
- "%s", pdev->dev->device_name);
+ "%s", pdev->info.device_name);
VkPhysicalDeviceVulkan11Properties core_1_1 = {
.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
pdev->mem_types[0].propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT;
pdev->mem_types[0].heapIndex = 0;
- if (ndev->vram_size) {
+ if (pdev->info.vram_size_B) {
pdev->mem_type_cnt = 2;
pdev->mem_heap_cnt = 2;
- pdev->mem_heaps[0].size = ndev->vram_size;
+ pdev->mem_heaps[0].size = pdev->info.vram_size_B;
pdev->mem_heaps[1].size = ndev->gart_size;
pdev->mem_heaps[1].flags = 0;
pdev->mem_types[1].heapIndex = 1;
gl_shader_stage stage)
{
enum pipe_shader_type p_stage = pipe_shader_type_from_mesa(stage);
- return nv50_ir_nir_shader_compiler_options(pdev->dev->chipset, p_stage);
+ return nv50_ir_nir_shader_compiler_options(pdev->info.chipset, p_stage);
}
struct spirv_to_nir_options
return false;
info->type = pipe_shader_type_from_mesa(nir->info.stage);
- info->target = pdev->dev->chipset;
+ info->target = pdev->info.chipset;
info->bin.nir = nir;
for (unsigned i = 0; i < 3; i++)
if (ret)
return ret;
- dev->chipset = args.info.chipset;
- dev->vram_size = args.info.ram_user;
+ dev->info.chipset = args.info.chipset;
+ dev->info.vram_size_B = args.info.ram_user;
switch (args.info.platform) {
case NV_DEVICE_INFO_V0_IGP:
break;
}
- dev->chipset_name = strndup(args.info.chip, sizeof(args.info.chip));
- dev->device_name = strndup(args.info.name, sizeof(args.info.name));
+ STATIC_ASSERT(sizeof(dev->info.device_name) >= sizeof(args.info.name));
+ memcpy(dev->info.device_name, args.info.name, sizeof(args.info.name));
+
+ STATIC_ASSERT(sizeof(dev->info.chipset_name) >= sizeof(args.info.chip));
+ memcpy(dev->info.chipset_name, args.info.chip, sizeof(args.info.chip));
return 0;
}
if (nouveau_ws_device_alloc(fd, device))
goto out_err;
- if (nouveau_ws_device_info(fd, device))
- goto out_err;
-
if (nouveau_ws_param(fd, NOUVEAU_GETPARAM_PCI_DEVICE, &value))
goto out_err;
- device->device_id = value;
device->info.device_id = value;
+
+ if (nouveau_ws_device_info(fd, device))
+ goto out_err;
+
if (drm_device->bustype == DRM_BUS_PCI) {
assert(device->info.type == NV_DEVICE_TYPE_DIS);
assert(device->info.device_id == drm_device->deviceinfo.pci->device_id);
if (nouveau_ws_param(fd, NOUVEAU_GETPARAM_AGP_SIZE, &value))
goto out_err;
+
os_get_available_system_memory(&device->gart_size);
device->gart_size = MIN2(device->gart_size, value);
device->fd = fd;
- device->vendor_id = 0x10de;
- device->sm = sm_for_chipset(device->chipset);
- device->is_integrated = device->vram_size == 0;
- if (device->vram_size == 0)
+ if (device->info.vram_size_B == 0)
device->local_mem_domain = NOUVEAU_GEM_DOMAIN_GART;
else
device->local_mem_domain = NOUVEAU_GEM_DOMAIN_VRAM;
if (nouveau_ws_context_create(device, &tmp_ctx))
goto out_err;
+ device->info.sm = sm_for_chipset(device->info.chipset);
device->info.cls_copy = tmp_ctx->copy.cls;
device->info.cls_eng2d = tmp_ctx->eng2d.cls;
device->info.cls_eng3d = tmp_ctx->eng3d.cls;
_mesa_hash_table_destroy(device->bos, NULL);
simple_mtx_destroy(&device->bos_lock);
close(device->fd);
- FREE(device->chipset_name);
- FREE(device->device_name);
FREE(device);
}
struct nouveau_ws_device {
int fd;
- uint16_t vendor_id;
- uint16_t device_id;
- uint32_t chipset;
-
struct nv_device_info info;
- char *chipset_name;
- char *device_name;
-
- /* maps to CUDAs Compute capability version */
- uint8_t sm;
-
- uint64_t vram_size;
uint64_t gart_size;
- bool is_integrated;
uint32_t local_mem_domain;
uint8_t gpc_count;