drm/i915/reg: stop using implicit dev_priv in DSPCLK_GATE_D

Remove the implicit dev_priv usage in DSPCLK_GATE_D register, and pass
it as parameter.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/41ca83573ca2d94bea568058f8cb8c35e814f8b1.1661855191.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index c8b741dd05bae0ecd1216282cd31352d0115a0c5..29cc05c04c65cff83d13ee22bf49f33af02376b2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1157,10 +1157,10 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
         * (and never recovering) in this case. intel_dsi_post_disable() will
         * clear it when we turn off the display.
         */
-       val = intel_de_read(dev_priv, DSPCLK_GATE_D);
+       val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
        val &= DPOUNIT_CLOCK_GATE_DISABLE;
        val |= VRHUNIT_CLOCK_GATE_DISABLE;
-       intel_de_write(dev_priv, DSPCLK_GATE_D, val);
+       intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
 
        /*
         * Disable trickle feed and enable pnd deadline calculation

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 9e9691e2a45af91cb88a6aedf136e6dbc3b7ca3f..0656d1b9249385cad83f144ad53b9dcb469ad0aa 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -183,12 +183,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
        u32 val;
 
        /* When using bit bashing for I2C, this bit needs to be set to 1 */
-       val = intel_de_read(dev_priv, DSPCLK_GATE_D);
+       val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
        if (!enable)
                val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
        else
                val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
-       intel_de_write(dev_priv, DSPCLK_GATE_D, val);
+       intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
 }
 
 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 6f26f7f91925d5177363ecdd969189b46f4ef3b0..c12bdca8da9ba60b0ccc55ce30e49ad1e7a43102 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -211,9 +211,9 @@ static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 
        /* WA_OVERLAY_CLKGATE:alm */
        if (enable)
-               intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
+               intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0);
        else
-               intel_de_write(dev_priv, DSPCLK_GATE_D,
+               intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv),
                               OVRUNIT_CLOCK_GATE_DISABLE);
 
        /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 233d0a8902ec137ad78fd10392a8bd3417645223..0bb4ac01634516735e11ddc9fe08d28ea0ee611e 100644 (file)
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -822,9 +822,9 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
                u32 val;
 
                /* Disable DPOunit clock gating, can stall pipe */
-               val = intel_de_read(dev_priv, DSPCLK_GATE_D);
+               val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
                val |= DPOUNIT_CLOCK_GATE_DISABLE;
-               intel_de_write(dev_priv, DSPCLK_GATE_D, val);
+               intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
        }
 
        if (!IS_GEMINILAKE(dev_priv))
@@ -998,9 +998,9 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
 
                vlv_dsi_pll_disable(encoder);
 
-               val = intel_de_read(dev_priv, DSPCLK_GATE_D);
+               val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
                val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
-               intel_de_write(dev_priv, DSPCLK_GATE_D, val);
+               intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
        }
 
        /* Assert reset */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8739abcc90e0af6f3373ff4aae0ebff564a7fb2..5e6239864c35817b73a7b764e11b9ea41928b911 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1637,7 +1637,7 @@
 #define  DSTATE_PLL_D3_OFF                     (1 << 3)
 #define  DSTATE_GFX_CLOCK_GATING               (1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING               (1 << 0)
-#define DSPCLK_GATE_D  _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
+#define DSPCLK_GATE_D(__i915)          _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
 # define DPUNIT_B_CLOCK_GATE_DISABLE           (1 << 30) /* 965 */
 # define VSUNIT_CLOCK_GATE_DISABLE             (1 << 29) /* 965 */
 # define VRHUNIT_CLOCK_GATE_DISABLE            (1 << 28) /* 965 */

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 76d1c5f9460013221bbac328e7eb3d8236ba300a..4aad010bd9b4dc4f64837e96553b686fea9ba876 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7994,7 +7994,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
                OVCUNIT_CLOCK_GATE_DISABLE;
        if (IS_GM45(dev_priv))
                dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
-       intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
+       intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D(dev_priv), dspclk_gate);
 
        g4x_disable_trickle_feed(dev_priv);
 }
@@ -8005,7 +8005,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
 
        intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
        intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
-       intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
+       intel_uncore_write(uncore, DSPCLK_GATE_D(dev_priv), 0);
        intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
        intel_uncore_write16(uncore, DEUC, 0);
        intel_uncore_write(uncore,